From patchwork Mon Jul 1 06:26:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Animesh Manna X-Patchwork-Id: 11025089 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7FB9F138B for ; Mon, 1 Jul 2019 06:35:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8192E1FFE6 for ; Mon, 1 Jul 2019 06:35:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7297B20502; Mon, 1 Jul 2019 06:35:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 256941FFE6 for ; Mon, 1 Jul 2019 06:35:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A0A189E23; Mon, 1 Jul 2019 06:35:46 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4657389F5B for ; Mon, 1 Jul 2019 06:35:45 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Jun 2019 23:34:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,437,1557212400"; d="scan'208";a="153988617" Received: from amanna.iind.intel.com ([10.223.74.216]) by orsmga007.jf.intel.com with ESMTP; 30 Jun 2019 23:34:01 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Mon, 1 Jul 2019 11:56:20 +0530 Message-Id: <20190701062632.456-4-animesh.manna@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190701062632.456-1-animesh.manna@intel.com> References: <20190701062632.456-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 03/15] drm/i915/dsb: single register write function for DSB. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP DSB support single register write through opcode 0x1. Generic api created which accumulate all single register write in a batch buffer and once DSB is triggered, it will program all the registers at the same time. Cc: Jani Nikula Cc: Rodrigo Vivi Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/intel_dsb.c | 36 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_dsb.h | 9 ++++++++ 2 files changed, 45 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dsb.c b/drivers/gpu/drm/i915/intel_dsb.c index de6a8a901d88..d9f51a28f8c4 100644 --- a/drivers/gpu/drm/i915/intel_dsb.c +++ b/drivers/gpu/drm/i915/intel_dsb.c @@ -8,6 +8,20 @@ #define DSB_BUF_SIZE (2 * PAGE_SIZE) +/* DSB opcodes. */ +#define DSB_OPCODE_SHIFT 24 +#define DSB_OPCODE_NOOP 0x0 +#define DSB_OPCODE_MMIO_WRITE 0x1 +#define DSB_OPCODE_WAIT_FOR_US 0x2 +#define DSB_OPCODE_WAIT_FOR_LINES 0x3 +#define DSB_OPCODE_WAIT_FOR_VBLANK 0x4 +#define DSB_OPCODE_WAIT_FOR_SL_IN 0x5 +#define DSB_OPCODE_WAIT_FOR_SL_OUT 0x6 +#define DSB_OPCODE_GENERATE_INT 0x7 +#define DSB_OPCODE_INDEXED_WRITE 0x9 +#define DSB_OPCODE_POLL 0xA +#define DSB_BYTE_EN (0xf << 20) + struct intel_dsb * intel_dsb_get(struct intel_crtc *crtc) { @@ -63,3 +77,25 @@ intel_dsb_get(struct intel_crtc *crtc) intel_runtime_pm_put(&i915->runtime_pm, wakeref); return dsb; } + +void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val) +{ + struct intel_crtc *crtc = dsb->crtc; + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + u32 *buf = dsb->cmd_buf; + + if (!buf) { + I915_WRITE(reg, val); + return; + } + + if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) { + DRM_DEBUG_KMS("DSB buffer overflow.\n"); + return; + } + + buf[dsb->free_pos++] = val; + buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << + DSB_OPCODE_SHIFT) | DSB_BYTE_EN | + i915_mmio_reg_offset(reg); +} diff --git a/drivers/gpu/drm/i915/intel_dsb.h b/drivers/gpu/drm/i915/intel_dsb.h index 50a2a6590a71..2015c372b0d5 100644 --- a/drivers/gpu/drm/i915/intel_dsb.h +++ b/drivers/gpu/drm/i915/intel_dsb.h @@ -6,6 +6,8 @@ #ifndef _INTEL_DSB_H #define _INTEL_DSB_H +#include "i915_reg.h" + struct intel_crtc; struct i915_vma; @@ -23,9 +25,16 @@ struct intel_dsb { u32 *cmd_buf; u32 cmd_buf_head; struct i915_vma *vma; + + /* + * free_pos will point the first free entry position + * and help in calculating cmd_buf_tail. + */ + int free_pos; }; struct intel_dsb * intel_dsb_get(struct intel_crtc *crtc); +void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val); #endif