| Message ID | 20190710005437.3496-9-daniele.ceraolospurio@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | GT-fy the uc code | expand |
On Wed, 10 Jul 2019 02:54:33 +0200, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> wrote: > Being part of the GT HW, it make sense to keep the guc/huc structures > inside the GT structure. To help with the encapsulation work done by the > following patches, both structures are placed inside a new intel_uc > container. Although this results in code with ugly nested dereferences > (i915->gt.uc.guc...), it saves us the extra work required in moving > the structures twice (i915 -> gt -> uc). The following patches will > reduce the number of places where we try to access the guc/huc > structures directly from i915 and reduce the ugliness. > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++ > drivers/gpu/drm/i915/gt/intel_reset.c | 6 +-- > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +- > drivers/gpu/drm/i915/gt/uc/intel_huc.c | 4 +- > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 52 +++++++++---------- > drivers/gpu/drm/i915/gt/uc/intel_uc.h | 5 ++ > drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 4 +- > drivers/gpu/drm/i915/i915_debugfs.c | 26 +++++----- > drivers/gpu/drm/i915/i915_drv.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 7 +-- > drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++-- > drivers/gpu/drm/i915/i915_irq.c | 6 +-- > drivers/gpu/drm/i915/intel_wopcm.c | 4 +- > 13 files changed, 69 insertions(+), 64 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h > b/drivers/gpu/drm/i915/gt/intel_gt_types.h > index 3563ce970102..b711252ff427 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h > @@ -13,6 +13,8 @@ > #include <linux/spinlock.h> > #include <linux/types.h> > +#include "uc/intel_uc.h" > + > #include "i915_vma.h" > #include "intel_wakeref.h" > @@ -25,6 +27,8 @@ struct intel_gt { > struct intel_uncore *uncore; > struct i915_ggtt *ggtt; > + struct intel_uc uc; > + > struct intel_gt_timelines { > struct mutex mutex; /* protects list */ > struct list_head active_list; > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c > b/drivers/gpu/drm/i915/gt/intel_reset.c > index 9abfa28c3020..ccedea636ba3 100644 > --- a/drivers/gpu/drm/i915/gt/intel_reset.c > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c > @@ -1109,14 +1109,14 @@ int i915_reset_engine(struct intel_engine_cs > *engine, const char *msg) > "Resetting %s for %s\n", engine->name, msg); > error->reset_engine_count[engine->id]++; > - if (!engine->i915->guc.execbuf_client) > + if (!engine->gt->uc.guc.execbuf_client) > ret = intel_gt_reset_engine(engine->i915, engine); > else > - ret = intel_guc_reset_engine(&engine->i915->guc, engine); > + ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine); > if (ret) { > /* If we fail here, we expect to fallback to a global reset */ > DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n", > - engine->i915->guc.execbuf_client ? "GuC " : "", > + engine->gt->uc.guc.execbuf_client ? "GuC " : "", maybe instead of doing 3x same deref, just add at the start: struct intel_guc *guc = &engine->gt->uc.guc; > engine->name, ret); > goto out; > } > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > index f015f7dee453..23906228b9b4 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > @@ -509,7 +509,7 @@ static void guc_submit(struct intel_engine_cs > *engine, > struct i915_request **out, > struct i915_request **end) > { > - struct intel_guc *guc = &engine->i915->guc; > + struct intel_guc *guc = &engine->gt->uc.guc; > struct intel_guc_client *client = guc->execbuf_client; > spin_lock(&client->wq_lock); > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c > b/drivers/gpu/drm/i915/gt/uc/intel_huc.c > index 2a41ee89a16d..581c9c3d4fc0 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c > @@ -47,7 +47,7 @@ void intel_huc_init_early(struct intel_huc *huc) > static int intel_huc_rsa_data_create(struct intel_huc *huc) > { > struct drm_i915_private *i915 = huc_to_i915(huc); > - struct intel_guc *guc = &i915->guc; > + struct intel_guc *guc = &i915->gt.uc.guc; maybe we can avoid i915/gt dance with: struct intel_guc *guc = huc_to_uc(huc)->guc; > struct i915_vma *vma; > void *vaddr; > @@ -113,7 +113,7 @@ void intel_huc_fini(struct intel_huc *huc) > int intel_huc_auth(struct intel_huc *huc) > { > struct drm_i915_private *i915 = huc_to_i915(huc); > - struct intel_guc *guc = &i915->guc; > + struct intel_guc *guc = &i915->gt.uc.guc; > int ret; > if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c > b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > index 6193b87855e0..e2080da2e1e4 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > @@ -54,8 +54,8 @@ static int __intel_uc_reset_hw(struct drm_i915_private > *dev_priv) > static int __get_platform_enable_guc(struct drm_i915_private *i915) > { > - struct intel_uc_fw *guc_fw = &i915->guc.fw; > - struct intel_uc_fw *huc_fw = &i915->huc.fw; > + struct intel_uc_fw *guc_fw = &i915->gt.uc.guc.fw; > + struct intel_uc_fw *huc_fw = &i915->gt.uc.huc.fw; maybe first add: struct intel_uc *uc = &i915->gt.uc; then struct intel_uc_fw *guc_fw = &uc->guc.fw; struct intel_uc_fw *huc_fw = &uc->huc.fw; > int enable_guc = 0; > /* Default is to use HuC if we know GuC and HuC firmwares */ > @@ -71,7 +71,7 @@ static int __get_default_guc_log_level(struct > drm_i915_private *i915) > { > int guc_log_level; > - if (!intel_uc_fw_supported(&i915->guc.fw) || > + if (!intel_uc_fw_supported(&i915->gt.uc.guc.fw) || > !intel_uc_is_using_guc(i915)) > guc_log_level = GUC_LOG_LEVEL_DISABLED; > else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) || > @@ -104,8 +104,8 @@ static int __get_default_guc_log_level(struct > drm_i915_private *i915) > */ > static void sanitize_options_early(struct drm_i915_private *i915) > { > - struct intel_uc_fw *guc_fw = &i915->guc.fw; > - struct intel_uc_fw *huc_fw = &i915->huc.fw; > + struct intel_uc_fw *guc_fw = &i915->gt.uc.guc.fw; > + struct intel_uc_fw *huc_fw = &i915->gt.uc.huc.fw; same here > /* A negative value means "use platform default" */ > if (i915_modparams.enable_guc < 0) > @@ -174,8 +174,8 @@ static void sanitize_options_early(struct > drm_i915_private *i915) > void intel_uc_init_early(struct drm_i915_private *i915) > { > - struct intel_guc *guc = &i915->guc; > - struct intel_huc *huc = &i915->huc; > + struct intel_guc *guc = &i915->gt.uc.guc; > + struct intel_huc *huc = &i915->gt.uc.huc; and here and in all other uc functions > intel_guc_init_early(guc); > intel_huc_init_early(huc); > @@ -185,7 +185,7 @@ void intel_uc_init_early(struct drm_i915_private > *i915) > void intel_uc_cleanup_early(struct drm_i915_private *i915) > { > - struct intel_guc *guc = &i915->guc; > + struct intel_guc *guc = &i915->gt.uc.guc; > guc_free_load_err_log(guc); > } > @@ -199,7 +199,7 @@ void intel_uc_cleanup_early(struct drm_i915_private > *i915) > */ > void intel_uc_init_mmio(struct drm_i915_private *i915) > { > - intel_guc_init_send_regs(&i915->guc); > + intel_guc_init_send_regs(&i915->gt.uc.guc); > } > static void guc_capture_load_err_log(struct intel_guc *guc) > @@ -351,10 +351,10 @@ void intel_uc_fetch_firmwares(struct > drm_i915_private *i915) > if (!USES_GUC(i915)) > return; > - intel_uc_fw_fetch(i915, &i915->guc.fw); > + intel_uc_fw_fetch(i915, &i915->gt.uc.guc.fw); > if (USES_HUC(i915)) > - intel_uc_fw_fetch(i915, &i915->huc.fw); > + intel_uc_fw_fetch(i915, &i915->gt.uc.huc.fw); > } > void intel_uc_cleanup_firmwares(struct drm_i915_private *i915) > @@ -363,15 +363,15 @@ void intel_uc_cleanup_firmwares(struct > drm_i915_private *i915) > return; > if (USES_HUC(i915)) > - intel_uc_fw_cleanup_fetch(&i915->huc.fw); > + intel_uc_fw_cleanup_fetch(&i915->gt.uc.huc.fw); > - intel_uc_fw_cleanup_fetch(&i915->guc.fw); > + intel_uc_fw_cleanup_fetch(&i915->gt.uc.guc.fw); > } > int intel_uc_init(struct drm_i915_private *i915) > { > - struct intel_guc *guc = &i915->guc; > - struct intel_huc *huc = &i915->huc; > + struct intel_guc *guc = &i915->gt.uc.guc; > + struct intel_huc *huc = &i915->gt.uc.huc; > int ret; > if (!USES_GUC(i915)) > @@ -415,7 +415,7 @@ int intel_uc_init(struct drm_i915_private *i915) > void intel_uc_fini(struct drm_i915_private *i915) > { > - struct intel_guc *guc = &i915->guc; > + struct intel_guc *guc = &i915->gt.uc.guc; > if (!USES_GUC(i915)) > return; > @@ -426,15 +426,15 @@ void intel_uc_fini(struct drm_i915_private *i915) > intel_guc_submission_fini(guc); > if (USES_HUC(i915)) > - intel_huc_fini(&i915->huc); > + intel_huc_fini(&i915->gt.uc.huc); > intel_guc_fini(guc); > } > static void __uc_sanitize(struct drm_i915_private *i915) > { > - struct intel_guc *guc = &i915->guc; > - struct intel_huc *huc = &i915->huc; > + struct intel_guc *guc = &i915->gt.uc.guc; > + struct intel_huc *huc = &i915->gt.uc.huc; > GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw)); > @@ -454,8 +454,8 @@ void intel_uc_sanitize(struct drm_i915_private *i915) > int intel_uc_init_hw(struct drm_i915_private *i915) > { > - struct intel_guc *guc = &i915->guc; > - struct intel_huc *huc = &i915->huc; > + struct intel_guc *guc = &i915->gt.uc.guc; > + struct intel_huc *huc = &i915->gt.uc.huc; > int ret, attempts; > if (!USES_GUC(i915)) > @@ -553,7 +553,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915) > void intel_uc_fini_hw(struct drm_i915_private *i915) > { > - struct intel_guc *guc = &i915->guc; > + struct intel_guc *guc = &i915->gt.uc.guc; > if (!intel_guc_is_loaded(guc)) > return; > @@ -575,7 +575,7 @@ void intel_uc_fini_hw(struct drm_i915_private *i915) > */ > void intel_uc_reset_prepare(struct drm_i915_private *i915) > { > - struct intel_guc *guc = &i915->guc; > + struct intel_guc *guc = &i915->gt.uc.guc; > if (!intel_guc_is_loaded(guc)) > return; > @@ -586,7 +586,7 @@ void intel_uc_reset_prepare(struct drm_i915_private > *i915) > void intel_uc_runtime_suspend(struct drm_i915_private *i915) > { > - struct intel_guc *guc = &i915->guc; > + struct intel_guc *guc = &i915->gt.uc.guc; > int err; > if (!intel_guc_is_loaded(guc)) > @@ -601,7 +601,7 @@ void intel_uc_runtime_suspend(struct > drm_i915_private *i915) > void intel_uc_suspend(struct drm_i915_private *i915) > { > - struct intel_guc *guc = &i915->guc; > + struct intel_guc *guc = &i915->gt.uc.guc; > intel_wakeref_t wakeref; > if (!intel_guc_is_loaded(guc)) > @@ -613,7 +613,7 @@ void intel_uc_suspend(struct drm_i915_private *i915) > int intel_uc_resume(struct drm_i915_private *i915) > { > - struct intel_guc *guc = &i915->guc; > + struct intel_guc *guc = &i915->gt.uc.guc; > int err; > if (!intel_guc_is_loaded(guc)) > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h > b/drivers/gpu/drm/i915/gt/uc/intel_uc.h > index 5a1383e192dd..a2fdc84afff2 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h > @@ -28,6 +28,11 @@ > #include "intel_huc.h" > #include "i915_params.h" > +struct intel_uc { > + struct intel_guc guc; > + struct intel_huc huc; > +}; > + > void intel_uc_init_early(struct drm_i915_private *dev_priv); > void intel_uc_cleanup_early(struct drm_i915_private *dev_priv); > void intel_uc_init_mmio(struct drm_i915_private *dev_priv); > diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c > b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c > index 6ca76f5a98d4..93f7c930ab18 100644 > --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c > +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c > @@ -138,7 +138,7 @@ static int igt_guc_clients(void *args) > mutex_lock(&dev_priv->drm.struct_mutex); > wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); > - guc = &dev_priv->guc; > + guc = &dev_priv->gt.uc.guc; > if (!guc) { > pr_err("No guc object!\n"); > err = -EINVAL; > @@ -230,7 +230,7 @@ static int igt_guc_doorbells(void *arg) > mutex_lock(&dev_priv->drm.struct_mutex); > wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); > - guc = &dev_priv->guc; > + guc = &dev_priv->gt.uc.guc; > if (!guc) { > pr_err("No guc object!\n"); > err = -EINVAL; > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > b/drivers/gpu/drm/i915/i915_debugfs.c > index c00ccd736dea..f082d54b0b75 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1885,7 +1885,7 @@ static int i915_huc_load_status_info(struct > seq_file *m, void *data) > return -ENODEV; > p = drm_seq_file_printer(m); > - intel_uc_fw_dump(&dev_priv->huc.fw, &p); > + intel_uc_fw_dump(&dev_priv->gt.uc.huc.fw, &p); > with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) > seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); > @@ -1903,7 +1903,7 @@ static int i915_guc_load_status_info(struct > seq_file *m, void *data) > return -ENODEV; > p = drm_seq_file_printer(m); > - intel_uc_fw_dump(&dev_priv->guc.fw, &p); > + intel_uc_fw_dump(&dev_priv->gt.uc.guc.fw, &p); > with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { > u32 tmp = I915_READ(GUC_STATUS); > @@ -1946,7 +1946,7 @@ stringify_guc_log_type(enum guc_log_buffer_type > type) > static void i915_guc_log_info(struct seq_file *m, > struct drm_i915_private *dev_priv) > { > - struct intel_guc_log *log = &dev_priv->guc.log; > + struct intel_guc_log *log = &dev_priv->gt.uc.guc.log; > enum guc_log_buffer_type type; > if (!intel_guc_log_relay_enabled(log)) { > @@ -1992,7 +1992,7 @@ static void i915_guc_client_info(struct seq_file > *m, > static int i915_guc_info(struct seq_file *m, void *data) > { > struct drm_i915_private *dev_priv = node_to_i915(m->private); > - const struct intel_guc *guc = &dev_priv->guc; > + const struct intel_guc *guc = &dev_priv->gt.uc.guc; > if (!USES_GUC(dev_priv)) > return -ENODEV; > @@ -2019,7 +2019,7 @@ static int i915_guc_info(struct seq_file *m, void > *data) > static int i915_guc_stage_pool(struct seq_file *m, void *data) > { > struct drm_i915_private *dev_priv = node_to_i915(m->private); > - const struct intel_guc *guc = &dev_priv->guc; > + const struct intel_guc *guc = &dev_priv->gt.uc.guc; > struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr; > intel_engine_mask_t tmp; > int index; > @@ -2082,9 +2082,9 @@ static int i915_guc_log_dump(struct seq_file *m, > void *data) > return -ENODEV; > if (dump_load_err) > - obj = dev_priv->guc.load_err_log; > - else if (dev_priv->guc.log.vma) > - obj = dev_priv->guc.log.vma->obj; > + obj = dev_priv->gt.uc.guc.load_err_log; > + else if (dev_priv->gt.uc.guc.log.vma) > + obj = dev_priv->gt.uc.guc.log.vma->obj; > if (!obj) > return 0; > @@ -2115,7 +2115,7 @@ static int i915_guc_log_level_get(void *data, u64 > *val) > if (!USES_GUC(dev_priv)) > return -ENODEV; > - *val = intel_guc_log_get_level(&dev_priv->guc.log); > + *val = intel_guc_log_get_level(&dev_priv->gt.uc.guc.log); > return 0; > } > @@ -2127,7 +2127,7 @@ static int i915_guc_log_level_set(void *data, u64 > val) > if (!USES_GUC(dev_priv)) > return -ENODEV; > - return intel_guc_log_set_level(&dev_priv->guc.log, val); > + return intel_guc_log_set_level(&dev_priv->gt.uc.guc.log, val); > } > DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops, > @@ -2141,9 +2141,9 @@ static int i915_guc_log_relay_open(struct inode > *inode, struct file *file) > if (!USES_GUC(dev_priv)) > return -ENODEV; > - file->private_data = &dev_priv->guc.log; > + file->private_data = &dev_priv->gt.uc.guc.log; > - return intel_guc_log_relay_open(&dev_priv->guc.log); > + return intel_guc_log_relay_open(&dev_priv->gt.uc.guc.log); > } > static ssize_t > @@ -2163,7 +2163,7 @@ static int i915_guc_log_relay_release(struct inode > *inode, struct file *file) > { > struct drm_i915_private *dev_priv = inode->i_private; > - intel_guc_log_relay_close(&dev_priv->guc.log); > + intel_guc_log_relay_close(&dev_priv->gt.uc.guc.log); > return 0; > } > diff --git a/drivers/gpu/drm/i915/i915_drv.c > b/drivers/gpu/drm/i915/i915_drv.c > index 4a8d90304e21..e7c89d320375 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -420,7 +420,7 @@ static int i915_getparam_ioctl(struct drm_device > *dev, void *data, > value = sseu->min_eu_in_pool; > break; > case I915_PARAM_HUC_STATUS: > - value = intel_huc_check_status(&dev_priv->huc); > + value = intel_huc_check_status(&dev_priv->gt.uc.huc); > if (value < 0) > return value; > break; > diff --git a/drivers/gpu/drm/i915/i915_drv.h > b/drivers/gpu/drm/i915/i915_drv.h > index b172d9ee3041..c4757cbf9a33 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1348,9 +1348,6 @@ struct drm_i915_private { > struct intel_wopcm wopcm; > - struct intel_huc huc; > - struct intel_guc guc; > - > struct intel_csr csr; > struct intel_gmbus gmbus[GMBUS_NUM_PINS]; > @@ -1907,12 +1904,12 @@ static inline struct drm_i915_private > *wopcm_to_i915(struct intel_wopcm *wopcm) > static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) > { > - return container_of(guc, struct drm_i915_private, guc); > + return container_of(guc, struct drm_i915_private, gt.uc.guc); > } > static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc) > { > - return container_of(huc, struct drm_i915_private, huc); > + return container_of(huc, struct drm_i915_private, gt.uc.huc); > } > /* Simple iterator over all initialised engines */ > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c > b/drivers/gpu/drm/i915/i915_gpu_error.c > index 5489cd879315..78e388fa059c 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -1552,21 +1552,22 @@ static void capture_uc_state(struct > i915_gpu_state *error) > { > struct drm_i915_private *i915 = error->i915; > struct i915_error_uc *error_uc = &error->uc; > + struct intel_uc *uc = &i915->gt.uc; > /* Capturing uC state won't be useful if there is no GuC */ > if (!error->device_info.has_guc) > return; > - error_uc->guc_fw = i915->guc.fw; > - error_uc->huc_fw = i915->huc.fw; > + error_uc->guc_fw = uc->guc.fw; > + error_uc->huc_fw = uc->huc.fw; > /* Non-default firmware paths will be specified by the modparam. > * As modparams are generally accesible from the userspace make > * explicit copies of the firmware paths. > */ > - error_uc->guc_fw.path = kstrdup(i915->guc.fw.path, GFP_ATOMIC); > - error_uc->huc_fw.path = kstrdup(i915->huc.fw.path, GFP_ATOMIC); > - error_uc->guc_log = i915_error_object_create(i915, i915->guc.log.vma); > + error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, GFP_ATOMIC); > + error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, GFP_ATOMIC); > + error_uc->guc_log = i915_error_object_create(i915, uc->guc.log.vma); > } > /* Capture all registers which don't fit into another category. */ > diff --git a/drivers/gpu/drm/i915/i915_irq.c > b/drivers/gpu/drm/i915/i915_irq.c > index 42d6d8bfac70..78c748cb9df8 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1655,7 +1655,7 @@ static void gen8_gt_irq_handler(struct > drm_i915_private *i915, > if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) { > gen6_rps_irq_handler(i915, gt_iir[2]); > - guc_irq_handler(&i915->guc, gt_iir[2] >> 16); > + guc_irq_handler(&i915->gt.uc.guc, gt_iir[2] >> 16); > } > } > @@ -3082,10 +3082,8 @@ static void > gen11_other_irq_handler(struct intel_gt *gt, const u8 instance, > const u16 iir) > { > - struct drm_i915_private *i915 = gt->i915; > - > if (instance == OTHER_GUC_INSTANCE) > - return guc_irq_handler(&i915->guc, iir); > + return guc_irq_handler(>->uc.guc, iir); > if (instance == OTHER_GTPM_INSTANCE) > return gen11_rps_irq_handler(gt, iir); > diff --git a/drivers/gpu/drm/i915/intel_wopcm.c > b/drivers/gpu/drm/i915/intel_wopcm.c > index 8c850785e4b4..0c05c5e6c7be 100644 > --- a/drivers/gpu/drm/i915/intel_wopcm.c > +++ b/drivers/gpu/drm/i915/intel_wopcm.c > @@ -164,8 +164,8 @@ static inline int check_hw_restriction(struct > drm_i915_private *i915, > int intel_wopcm_init(struct intel_wopcm *wopcm) > { > struct drm_i915_private *i915 = wopcm_to_i915(wopcm); > - u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->guc.fw); > - u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->huc.fw); > + u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->gt.uc.guc.fw); > + u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->gt.uc.huc.fw); > u32 ctx_rsvd = context_reserved_size(i915); > u32 guc_wopcm_base; > u32 guc_wopcm_size;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 3563ce970102..b711252ff427 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -13,6 +13,8 @@ #include <linux/spinlock.h> #include <linux/types.h> +#include "uc/intel_uc.h" + #include "i915_vma.h" #include "intel_wakeref.h" @@ -25,6 +27,8 @@ struct intel_gt { struct intel_uncore *uncore; struct i915_ggtt *ggtt; + struct intel_uc uc; + struct intel_gt_timelines { struct mutex mutex; /* protects list */ struct list_head active_list; diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 9abfa28c3020..ccedea636ba3 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -1109,14 +1109,14 @@ int i915_reset_engine(struct intel_engine_cs *engine, const char *msg) "Resetting %s for %s\n", engine->name, msg); error->reset_engine_count[engine->id]++; - if (!engine->i915->guc.execbuf_client) + if (!engine->gt->uc.guc.execbuf_client) ret = intel_gt_reset_engine(engine->i915, engine); else - ret = intel_guc_reset_engine(&engine->i915->guc, engine); + ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine); if (ret) { /* If we fail here, we expect to fallback to a global reset */ DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n", - engine->i915->guc.execbuf_client ? "GuC " : "", + engine->gt->uc.guc.execbuf_client ? "GuC " : "", engine->name, ret); goto out; } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index f015f7dee453..23906228b9b4 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -509,7 +509,7 @@ static void guc_submit(struct intel_engine_cs *engine, struct i915_request **out, struct i915_request **end) { - struct intel_guc *guc = &engine->i915->guc; + struct intel_guc *guc = &engine->gt->uc.guc; struct intel_guc_client *client = guc->execbuf_client; spin_lock(&client->wq_lock); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c index 2a41ee89a16d..581c9c3d4fc0 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@ -47,7 +47,7 @@ void intel_huc_init_early(struct intel_huc *huc) static int intel_huc_rsa_data_create(struct intel_huc *huc) { struct drm_i915_private *i915 = huc_to_i915(huc); - struct intel_guc *guc = &i915->guc; + struct intel_guc *guc = &i915->gt.uc.guc; struct i915_vma *vma; void *vaddr; @@ -113,7 +113,7 @@ void intel_huc_fini(struct intel_huc *huc) int intel_huc_auth(struct intel_huc *huc) { struct drm_i915_private *i915 = huc_to_i915(huc); - struct intel_guc *guc = &i915->guc; + struct intel_guc *guc = &i915->gt.uc.guc; int ret; if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index 6193b87855e0..e2080da2e1e4 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -54,8 +54,8 @@ static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv) static int __get_platform_enable_guc(struct drm_i915_private *i915) { - struct intel_uc_fw *guc_fw = &i915->guc.fw; - struct intel_uc_fw *huc_fw = &i915->huc.fw; + struct intel_uc_fw *guc_fw = &i915->gt.uc.guc.fw; + struct intel_uc_fw *huc_fw = &i915->gt.uc.huc.fw; int enable_guc = 0; /* Default is to use HuC if we know GuC and HuC firmwares */ @@ -71,7 +71,7 @@ static int __get_default_guc_log_level(struct drm_i915_private *i915) { int guc_log_level; - if (!intel_uc_fw_supported(&i915->guc.fw) || + if (!intel_uc_fw_supported(&i915->gt.uc.guc.fw) || !intel_uc_is_using_guc(i915)) guc_log_level = GUC_LOG_LEVEL_DISABLED; else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) || @@ -104,8 +104,8 @@ static int __get_default_guc_log_level(struct drm_i915_private *i915) */ static void sanitize_options_early(struct drm_i915_private *i915) { - struct intel_uc_fw *guc_fw = &i915->guc.fw; - struct intel_uc_fw *huc_fw = &i915->huc.fw; + struct intel_uc_fw *guc_fw = &i915->gt.uc.guc.fw; + struct intel_uc_fw *huc_fw = &i915->gt.uc.huc.fw; /* A negative value means "use platform default" */ if (i915_modparams.enable_guc < 0) @@ -174,8 +174,8 @@ static void sanitize_options_early(struct drm_i915_private *i915) void intel_uc_init_early(struct drm_i915_private *i915) { - struct intel_guc *guc = &i915->guc; - struct intel_huc *huc = &i915->huc; + struct intel_guc *guc = &i915->gt.uc.guc; + struct intel_huc *huc = &i915->gt.uc.huc; intel_guc_init_early(guc); intel_huc_init_early(huc); @@ -185,7 +185,7 @@ void intel_uc_init_early(struct drm_i915_private *i915) void intel_uc_cleanup_early(struct drm_i915_private *i915) { - struct intel_guc *guc = &i915->guc; + struct intel_guc *guc = &i915->gt.uc.guc; guc_free_load_err_log(guc); } @@ -199,7 +199,7 @@ void intel_uc_cleanup_early(struct drm_i915_private *i915) */ void intel_uc_init_mmio(struct drm_i915_private *i915) { - intel_guc_init_send_regs(&i915->guc); + intel_guc_init_send_regs(&i915->gt.uc.guc); } static void guc_capture_load_err_log(struct intel_guc *guc) @@ -351,10 +351,10 @@ void intel_uc_fetch_firmwares(struct drm_i915_private *i915) if (!USES_GUC(i915)) return; - intel_uc_fw_fetch(i915, &i915->guc.fw); + intel_uc_fw_fetch(i915, &i915->gt.uc.guc.fw); if (USES_HUC(i915)) - intel_uc_fw_fetch(i915, &i915->huc.fw); + intel_uc_fw_fetch(i915, &i915->gt.uc.huc.fw); } void intel_uc_cleanup_firmwares(struct drm_i915_private *i915) @@ -363,15 +363,15 @@ void intel_uc_cleanup_firmwares(struct drm_i915_private *i915) return; if (USES_HUC(i915)) - intel_uc_fw_cleanup_fetch(&i915->huc.fw); + intel_uc_fw_cleanup_fetch(&i915->gt.uc.huc.fw); - intel_uc_fw_cleanup_fetch(&i915->guc.fw); + intel_uc_fw_cleanup_fetch(&i915->gt.uc.guc.fw); } int intel_uc_init(struct drm_i915_private *i915) { - struct intel_guc *guc = &i915->guc; - struct intel_huc *huc = &i915->huc; + struct intel_guc *guc = &i915->gt.uc.guc; + struct intel_huc *huc = &i915->gt.uc.huc; int ret; if (!USES_GUC(i915)) @@ -415,7 +415,7 @@ int intel_uc_init(struct drm_i915_private *i915) void intel_uc_fini(struct drm_i915_private *i915) { - struct intel_guc *guc = &i915->guc; + struct intel_guc *guc = &i915->gt.uc.guc; if (!USES_GUC(i915)) return; @@ -426,15 +426,15 @@ void intel_uc_fini(struct drm_i915_private *i915) intel_guc_submission_fini(guc); if (USES_HUC(i915)) - intel_huc_fini(&i915->huc); + intel_huc_fini(&i915->gt.uc.huc); intel_guc_fini(guc); } static void __uc_sanitize(struct drm_i915_private *i915) { - struct intel_guc *guc = &i915->guc; - struct intel_huc *huc = &i915->huc; + struct intel_guc *guc = &i915->gt.uc.guc; + struct intel_huc *huc = &i915->gt.uc.huc; GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw)); @@ -454,8 +454,8 @@ void intel_uc_sanitize(struct drm_i915_private *i915) int intel_uc_init_hw(struct drm_i915_private *i915) { - struct intel_guc *guc = &i915->guc; - struct intel_huc *huc = &i915->huc; + struct intel_guc *guc = &i915->gt.uc.guc; + struct intel_huc *huc = &i915->gt.uc.huc; int ret, attempts; if (!USES_GUC(i915)) @@ -553,7 +553,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915) void intel_uc_fini_hw(struct drm_i915_private *i915) { - struct intel_guc *guc = &i915->guc; + struct intel_guc *guc = &i915->gt.uc.guc; if (!intel_guc_is_loaded(guc)) return; @@ -575,7 +575,7 @@ void intel_uc_fini_hw(struct drm_i915_private *i915) */ void intel_uc_reset_prepare(struct drm_i915_private *i915) { - struct intel_guc *guc = &i915->guc; + struct intel_guc *guc = &i915->gt.uc.guc; if (!intel_guc_is_loaded(guc)) return; @@ -586,7 +586,7 @@ void intel_uc_reset_prepare(struct drm_i915_private *i915) void intel_uc_runtime_suspend(struct drm_i915_private *i915) { - struct intel_guc *guc = &i915->guc; + struct intel_guc *guc = &i915->gt.uc.guc; int err; if (!intel_guc_is_loaded(guc)) @@ -601,7 +601,7 @@ void intel_uc_runtime_suspend(struct drm_i915_private *i915) void intel_uc_suspend(struct drm_i915_private *i915) { - struct intel_guc *guc = &i915->guc; + struct intel_guc *guc = &i915->gt.uc.guc; intel_wakeref_t wakeref; if (!intel_guc_is_loaded(guc)) @@ -613,7 +613,7 @@ void intel_uc_suspend(struct drm_i915_private *i915) int intel_uc_resume(struct drm_i915_private *i915) { - struct intel_guc *guc = &i915->guc; + struct intel_guc *guc = &i915->gt.uc.guc; int err; if (!intel_guc_is_loaded(guc)) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h index 5a1383e192dd..a2fdc84afff2 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h @@ -28,6 +28,11 @@ #include "intel_huc.h" #include "i915_params.h" +struct intel_uc { + struct intel_guc guc; + struct intel_huc huc; +}; + void intel_uc_init_early(struct drm_i915_private *dev_priv); void intel_uc_cleanup_early(struct drm_i915_private *dev_priv); void intel_uc_init_mmio(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c index 6ca76f5a98d4..93f7c930ab18 100644 --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c @@ -138,7 +138,7 @@ static int igt_guc_clients(void *args) mutex_lock(&dev_priv->drm.struct_mutex); wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); - guc = &dev_priv->guc; + guc = &dev_priv->gt.uc.guc; if (!guc) { pr_err("No guc object!\n"); err = -EINVAL; @@ -230,7 +230,7 @@ static int igt_guc_doorbells(void *arg) mutex_lock(&dev_priv->drm.struct_mutex); wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); - guc = &dev_priv->guc; + guc = &dev_priv->gt.uc.guc; if (!guc) { pr_err("No guc object!\n"); err = -EINVAL; diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index c00ccd736dea..f082d54b0b75 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1885,7 +1885,7 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data) return -ENODEV; p = drm_seq_file_printer(m); - intel_uc_fw_dump(&dev_priv->huc.fw, &p); + intel_uc_fw_dump(&dev_priv->gt.uc.huc.fw, &p); with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); @@ -1903,7 +1903,7 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data) return -ENODEV; p = drm_seq_file_printer(m); - intel_uc_fw_dump(&dev_priv->guc.fw, &p); + intel_uc_fw_dump(&dev_priv->gt.uc.guc.fw, &p); with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { u32 tmp = I915_READ(GUC_STATUS); @@ -1946,7 +1946,7 @@ stringify_guc_log_type(enum guc_log_buffer_type type) static void i915_guc_log_info(struct seq_file *m, struct drm_i915_private *dev_priv) { - struct intel_guc_log *log = &dev_priv->guc.log; + struct intel_guc_log *log = &dev_priv->gt.uc.guc.log; enum guc_log_buffer_type type; if (!intel_guc_log_relay_enabled(log)) { @@ -1992,7 +1992,7 @@ static void i915_guc_client_info(struct seq_file *m, static int i915_guc_info(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); - const struct intel_guc *guc = &dev_priv->guc; + const struct intel_guc *guc = &dev_priv->gt.uc.guc; if (!USES_GUC(dev_priv)) return -ENODEV; @@ -2019,7 +2019,7 @@ static int i915_guc_info(struct seq_file *m, void *data) static int i915_guc_stage_pool(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); - const struct intel_guc *guc = &dev_priv->guc; + const struct intel_guc *guc = &dev_priv->gt.uc.guc; struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr; intel_engine_mask_t tmp; int index; @@ -2082,9 +2082,9 @@ static int i915_guc_log_dump(struct seq_file *m, void *data) return -ENODEV; if (dump_load_err) - obj = dev_priv->guc.load_err_log; - else if (dev_priv->guc.log.vma) - obj = dev_priv->guc.log.vma->obj; + obj = dev_priv->gt.uc.guc.load_err_log; + else if (dev_priv->gt.uc.guc.log.vma) + obj = dev_priv->gt.uc.guc.log.vma->obj; if (!obj) return 0; @@ -2115,7 +2115,7 @@ static int i915_guc_log_level_get(void *data, u64 *val) if (!USES_GUC(dev_priv)) return -ENODEV; - *val = intel_guc_log_get_level(&dev_priv->guc.log); + *val = intel_guc_log_get_level(&dev_priv->gt.uc.guc.log); return 0; } @@ -2127,7 +2127,7 @@ static int i915_guc_log_level_set(void *data, u64 val) if (!USES_GUC(dev_priv)) return -ENODEV; - return intel_guc_log_set_level(&dev_priv->guc.log, val); + return intel_guc_log_set_level(&dev_priv->gt.uc.guc.log, val); } DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops, @@ -2141,9 +2141,9 @@ static int i915_guc_log_relay_open(struct inode *inode, struct file *file) if (!USES_GUC(dev_priv)) return -ENODEV; - file->private_data = &dev_priv->guc.log; + file->private_data = &dev_priv->gt.uc.guc.log; - return intel_guc_log_relay_open(&dev_priv->guc.log); + return intel_guc_log_relay_open(&dev_priv->gt.uc.guc.log); } static ssize_t @@ -2163,7 +2163,7 @@ static int i915_guc_log_relay_release(struct inode *inode, struct file *file) { struct drm_i915_private *dev_priv = inode->i_private; - intel_guc_log_relay_close(&dev_priv->guc.log); + intel_guc_log_relay_close(&dev_priv->gt.uc.guc.log); return 0; } diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 4a8d90304e21..e7c89d320375 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -420,7 +420,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, value = sseu->min_eu_in_pool; break; case I915_PARAM_HUC_STATUS: - value = intel_huc_check_status(&dev_priv->huc); + value = intel_huc_check_status(&dev_priv->gt.uc.huc); if (value < 0) return value; break; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b172d9ee3041..c4757cbf9a33 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1348,9 +1348,6 @@ struct drm_i915_private { struct intel_wopcm wopcm; - struct intel_huc huc; - struct intel_guc guc; - struct intel_csr csr; struct intel_gmbus gmbus[GMBUS_NUM_PINS]; @@ -1907,12 +1904,12 @@ static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm) static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) { - return container_of(guc, struct drm_i915_private, guc); + return container_of(guc, struct drm_i915_private, gt.uc.guc); } static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc) { - return container_of(huc, struct drm_i915_private, huc); + return container_of(huc, struct drm_i915_private, gt.uc.huc); } /* Simple iterator over all initialised engines */ diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 5489cd879315..78e388fa059c 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1552,21 +1552,22 @@ static void capture_uc_state(struct i915_gpu_state *error) { struct drm_i915_private *i915 = error->i915; struct i915_error_uc *error_uc = &error->uc; + struct intel_uc *uc = &i915->gt.uc; /* Capturing uC state won't be useful if there is no GuC */ if (!error->device_info.has_guc) return; - error_uc->guc_fw = i915->guc.fw; - error_uc->huc_fw = i915->huc.fw; + error_uc->guc_fw = uc->guc.fw; + error_uc->huc_fw = uc->huc.fw; /* Non-default firmware paths will be specified by the modparam. * As modparams are generally accesible from the userspace make * explicit copies of the firmware paths. */ - error_uc->guc_fw.path = kstrdup(i915->guc.fw.path, GFP_ATOMIC); - error_uc->huc_fw.path = kstrdup(i915->huc.fw.path, GFP_ATOMIC); - error_uc->guc_log = i915_error_object_create(i915, i915->guc.log.vma); + error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, GFP_ATOMIC); + error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, GFP_ATOMIC); + error_uc->guc_log = i915_error_object_create(i915, uc->guc.log.vma); } /* Capture all registers which don't fit into another category. */ diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 42d6d8bfac70..78c748cb9df8 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1655,7 +1655,7 @@ static void gen8_gt_irq_handler(struct drm_i915_private *i915, if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) { gen6_rps_irq_handler(i915, gt_iir[2]); - guc_irq_handler(&i915->guc, gt_iir[2] >> 16); + guc_irq_handler(&i915->gt.uc.guc, gt_iir[2] >> 16); } } @@ -3082,10 +3082,8 @@ static void gen11_other_irq_handler(struct intel_gt *gt, const u8 instance, const u16 iir) { - struct drm_i915_private *i915 = gt->i915; - if (instance == OTHER_GUC_INSTANCE) - return guc_irq_handler(&i915->guc, iir); + return guc_irq_handler(>->uc.guc, iir); if (instance == OTHER_GTPM_INSTANCE) return gen11_rps_irq_handler(gt, iir); diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c index 8c850785e4b4..0c05c5e6c7be 100644 --- a/drivers/gpu/drm/i915/intel_wopcm.c +++ b/drivers/gpu/drm/i915/intel_wopcm.c @@ -164,8 +164,8 @@ static inline int check_hw_restriction(struct drm_i915_private *i915, int intel_wopcm_init(struct intel_wopcm *wopcm) { struct drm_i915_private *i915 = wopcm_to_i915(wopcm); - u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->guc.fw); - u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->huc.fw); + u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->gt.uc.guc.fw); + u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->gt.uc.huc.fw); u32 ctx_rsvd = context_reserved_size(i915); u32 guc_wopcm_base; u32 guc_wopcm_size;
Being part of the GT HW, it make sense to keep the guc/huc structures inside the GT structure. To help with the encapsulation work done by the following patches, both structures are placed inside a new intel_uc container. Although this results in code with ugly nested dereferences (i915->gt.uc.guc...), it saves us the extra work required in moving the structures twice (i915 -> gt -> uc). The following patches will reduce the number of places where we try to access the guc/huc structures directly from i915 and reduce the ugliness. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++ drivers/gpu/drm/i915/gt/intel_reset.c | 6 +-- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_huc.c | 4 +- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 52 +++++++++---------- drivers/gpu/drm/i915/gt/uc/intel_uc.h | 5 ++ drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 4 +- drivers/gpu/drm/i915/i915_debugfs.c | 26 +++++----- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 7 +-- drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++-- drivers/gpu/drm/i915/i915_irq.c | 6 +-- drivers/gpu/drm/i915/intel_wopcm.c | 4 +- 13 files changed, 69 insertions(+), 64 deletions(-)