| Message ID | 20190718145053.25808-3-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output | expand |
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Looks like we're currently setting the MSA to xvYCC BT.709 instead > of the YCbCr BT.601 claimed by the comment. But even that comment > is wrong since we configure the CSC matrix to BT.709. > > Let's remove the bogus statement from the comment and fix the > MSA to indicate YCbCr BT.709 so that it matches the actual > pixel data we're transmitting. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++-- > drivers/gpu/drm/i915/i915_reg.h | 3 ++- > 2 files changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 18bc0f2690c9..157c5851a688 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1730,10 +1730,12 @@ void intel_ddi_set_pipe_settings(const struct > intel_crtc_state *crtc_state) > /* > * As per DP 1.2 spec section 2.3.4.3 while sending > * YCBCR 444 signals we should program MSA MISC1/0 fields with > - * colorspace information. The output colorspace encoding is > BT601. > + * colorspace information. > */ > if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) > - temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR; > + temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR > | > + TRANS_MSA_YCBCR_BT709; > + > /* > * As per DP 1.4a spec section 2.2.4.3 [MSA Field for > Indication > * of Color Encoding Format and Content Color Gamut] while > sending > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index fdd9bc01e694..35133b2ef6c9 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9605,7 +9605,8 @@ enum skl_power_gate { > > #define TRANS_MSA_SYNC_CLK (1 << 0) > #define TRANS_MSA_SAMPLING_444 (2 << 1) > -#define TRANS_MSA_CLRSP_YCBCR (2 << 3) > +#define TRANS_MSA_CLRSP_YCBCR (1 << 3) > +#define TRANS_MSA_YCBCR_BT709 (1 << 4) > #define TRANS_MSA_6_BPC (0 << 5) > #define TRANS_MSA_8_BPC (1 << 5) > #define TRANS_MSA_10_BPC (2 << 5) The changes look good to me. Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 18bc0f2690c9..157c5851a688 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1730,10 +1730,12 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state) /* * As per DP 1.2 spec section 2.3.4.3 while sending * YCBCR 444 signals we should program MSA MISC1/0 fields with - * colorspace information. The output colorspace encoding is BT601. + * colorspace information. */ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) - temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR; + temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR | + TRANS_MSA_YCBCR_BT709; + /* * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication * of Color Encoding Format and Content Color Gamut] while sending diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fdd9bc01e694..35133b2ef6c9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9605,7 +9605,8 @@ enum skl_power_gate { #define TRANS_MSA_SYNC_CLK (1 << 0) #define TRANS_MSA_SAMPLING_444 (2 << 1) -#define TRANS_MSA_CLRSP_YCBCR (2 << 3) +#define TRANS_MSA_CLRSP_YCBCR (1 << 3) +#define TRANS_MSA_YCBCR_BT709 (1 << 4) #define TRANS_MSA_6_BPC (0 << 5) #define TRANS_MSA_8_BPC (1 << 5) #define TRANS_MSA_10_BPC (2 << 5)