From patchwork Fri Jul 26 00:12:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 11060071 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8450D912 for ; Fri, 26 Jul 2019 00:12:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 747BB200E5 for ; Fri, 26 Jul 2019 00:12:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 68BEA28A71; Fri, 26 Jul 2019 00:12:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 095BD200E5 for ; Fri, 26 Jul 2019 00:12:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DAF0F6E83C; Fri, 26 Jul 2019 00:12:20 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5E5A46E82C for ; Fri, 26 Jul 2019 00:12:17 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Jul 2019 17:12:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,308,1559545200"; d="scan'208";a="178181705" Received: from ldmartin-desk1.jf.intel.com (HELO ldmartin-desk1.intel.com) ([10.24.9.40]) by FMSMGA003.fm.intel.com with ESMTP; 25 Jul 2019 17:12:16 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Jul 2019 17:12:06 -0700 Message-Id: <20190726001208.6971-3-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190726001208.6971-1-lucas.demarchi@intel.com> References: <20190726001208.6971-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/tgl: Define MOCS entries for Tigerlake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mika Kuoppala Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tomasz Lis The MOCS table is published as part of bspec, and versioned. Entries are supposed to never be modified, but new ones can be added. Adding entries increases table version. The patch includes version 1 entries. Two of the 3 legacy entries used for gen9 are no longer expected to work. Although we are changing the gen11 table, those changes are supposed to be backward compatible since we are only touching previously undefined entries. v2: Add the missing entries in 49-51 range and replace "HW reserved" terminology to what it actually is: L1 is implicitly enabled (from Daniele) Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Daniele Ceraolo Spurio Signed-off-by: Tomasz Lis Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_mocs.c | 37 +++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 290a5e9b90b9..ca370c7487f9 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -62,6 +62,10 @@ struct drm_i915_mocs_table { #define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */ /* (e)LLC caching options */ +/* + * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means + * the same as LE_UC + */ #define LE_0_PAGETABLE _LE_CACHEABILITY(0) #define LE_1_UC _LE_CACHEABILITY(1) #define LE_2_WT _LE_CACHEABILITY(2) @@ -100,8 +104,9 @@ struct drm_i915_mocs_table { * of bspec. * * Entries not part of the following tables are undefined as far as - * userspace is concerned and shouldn't be relied upon. For the time - * being they will be initialized to PTE. + * userspace is concerned and shouldn't be relied upon. For Gen < 12 + * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for + * PTE. We use the same value, but that actually means Uncached. * * The last two entries are reserved by the hardware. For ICL+ they * should be initialized according to bspec and never used, for older @@ -137,11 +142,13 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { }; #define GEN11_MOCS_ENTRIES \ - /* Base - Uncached (Deprecated) */ \ + /* Gen11: Base - Uncached (Deprecated) */ \ + /* Gen12+: Base - Error (Reserved for Non-Use) */ \ MOCS_ENTRY(I915_MOCS_UNCACHED, \ LE_1_UC | LE_TC_1_LLC, \ L3_1_UC), \ /* Base - L3 + LeCC:PAT (Deprecated) */ \ + /* Gen12+: Base - Reserved */ \ MOCS_ENTRY(I915_MOCS_PTE, \ LE_0_PAGETABLE | LE_TC_1_LLC, \ L3_3_WB), \ @@ -233,6 +240,30 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { MOCS_ENTRY(23, \ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \ L3_3_WB), \ + /* Gen12+: Implicitly enable L1 - HDC:L1 + L3 + LLC */ \ + MOCS_ENTRY(48, \ + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ + L3_3_WB), \ + /* Gen12+: Implicitly enable L1 - HDC:L1 + L3 */ \ + MOCS_ENTRY(49, \ + LE_1_UC | LE_TC_1_LLC, \ + L3_3_WB), \ + /* Gen12+: Implicitly enable L1 - HDC:L1 + LLC */ \ + MOCS_ENTRY(50, \ + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ + L3_1_UC), \ + /* Gen12+: Implicitly enable L1 - HDC:L1 */ \ + MOCS_ENTRY(51, \ + LE_1_UC | LE_TC_1_LLC, \ + L3_1_UC), \ + /* Gen12+: HW Reserved - HW Special Case (CCS) */ \ + MOCS_ENTRY(60, \ + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ + L3_1_UC), \ + /* Gen12+: HW Reserved - HW Special Case (Displayable) */ \ + MOCS_ENTRY(61, \ + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \ + L3_3_WB), \ /* HW Reserved - SW program but never use */ \ MOCS_ENTRY(62, \ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \