| Message ID | 20190726155805.2736-3-michal.wajdeczko@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/3] drm/i915/uc: Remove redundant header_offset/size definitions | expand |
On 7/26/19 8:58 AM, Michal Wajdeczko wrote: > According to Firmware layout definition, RSA signature is located > after CSS header and uCode so actual RSA offset in the blob can be > easily calculated when needed (and we need it only once). > > Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Daniele > --- > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 8 +++----- > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 1 - > 2 files changed, 3 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > index 05079c59ae04..b0f2852dec41 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > @@ -238,7 +238,6 @@ void intel_uc_fw_fetch(struct intel_uc_fw *uc_fw, struct drm_i915_private *i915) > err = -ENOEXEC; > goto fail; > } > - uc_fw->rsa_offset = sizeof(struct uc_css_header) + uc_fw->ucode_size; > uc_fw->rsa_size = css->key_size_dw * sizeof(u32); > > /* At least, it should have header, uCode and RSA. Size of all three. */ > @@ -512,11 +511,11 @@ size_t intel_uc_fw_copy_rsa(struct intel_uc_fw *uc_fw, void *dst, u32 max_len) > { > struct sg_table *pages = uc_fw->obj->mm.pages; > u32 size = min_t(u32, uc_fw->rsa_size, max_len); > + u32 offset = sizeof(struct uc_css_header) + uc_fw->ucode_size; > > GEM_BUG_ON(!intel_uc_fw_is_available(uc_fw)); > > - return sg_pcopy_to_buffer(pages->sgl, pages->nents, > - dst, size, uc_fw->rsa_offset); > + return sg_pcopy_to_buffer(pages->sgl, pages->nents, dst, size, offset); > } > > /** > @@ -536,6 +535,5 @@ void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p) > uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted, > uc_fw->major_ver_found, uc_fw->minor_ver_found); > drm_printf(p, "\tuCode: %u bytes\n", uc_fw->ucode_size); > - drm_printf(p, "\tRSA: offset %u, size %u\n", > - uc_fw->rsa_offset, uc_fw->rsa_size); > + drm_printf(p, "\tRSA: %u bytes\n", uc_fw->rsa_size); > } > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h > index 6a04bc6d419f..c2ab2803715d 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h > @@ -75,7 +75,6 @@ struct intel_uc_fw { > u16 minor_ver_found; > > u32 rsa_size; > - u32 rsa_offset; > u32 ucode_size; > }; > >
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 05079c59ae04..b0f2852dec41 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -238,7 +238,6 @@ void intel_uc_fw_fetch(struct intel_uc_fw *uc_fw, struct drm_i915_private *i915) err = -ENOEXEC; goto fail; } - uc_fw->rsa_offset = sizeof(struct uc_css_header) + uc_fw->ucode_size; uc_fw->rsa_size = css->key_size_dw * sizeof(u32); /* At least, it should have header, uCode and RSA. Size of all three. */ @@ -512,11 +511,11 @@ size_t intel_uc_fw_copy_rsa(struct intel_uc_fw *uc_fw, void *dst, u32 max_len) { struct sg_table *pages = uc_fw->obj->mm.pages; u32 size = min_t(u32, uc_fw->rsa_size, max_len); + u32 offset = sizeof(struct uc_css_header) + uc_fw->ucode_size; GEM_BUG_ON(!intel_uc_fw_is_available(uc_fw)); - return sg_pcopy_to_buffer(pages->sgl, pages->nents, - dst, size, uc_fw->rsa_offset); + return sg_pcopy_to_buffer(pages->sgl, pages->nents, dst, size, offset); } /** @@ -536,6 +535,5 @@ void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p) uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted, uc_fw->major_ver_found, uc_fw->minor_ver_found); drm_printf(p, "\tuCode: %u bytes\n", uc_fw->ucode_size); - drm_printf(p, "\tRSA: offset %u, size %u\n", - uc_fw->rsa_offset, uc_fw->rsa_size); + drm_printf(p, "\tRSA: %u bytes\n", uc_fw->rsa_size); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h index 6a04bc6d419f..c2ab2803715d 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h @@ -75,7 +75,6 @@ struct intel_uc_fw { u16 minor_ver_found; u32 rsa_size; - u32 rsa_offset; u32 ucode_size; };
According to Firmware layout definition, RSA signature is located after CSS header and uCode so actual RSA offset in the blob can be easily calculated when needed (and we need it only once). Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 8 +++----- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 1 - 2 files changed, 3 insertions(+), 6 deletions(-)