From patchwork Wed Aug 21 06:32:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Animesh Manna X-Patchwork-Id: 11105559 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 195471399 for ; Wed, 21 Aug 2019 06:40:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 01F492087E for ; Wed, 21 Aug 2019 06:40:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 01F492087E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E2F576E90F; Wed, 21 Aug 2019 06:40:13 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 156186E90A for ; Wed, 21 Aug 2019 06:40:08 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Aug 2019 23:40:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,411,1559545200"; d="scan'208";a="195935643" Received: from amanna.iind.intel.com ([10.223.74.216]) by fmsmga001.fm.intel.com with ESMTP; 20 Aug 2019 23:40:06 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Wed, 21 Aug 2019 12:02:24 +0530 Message-Id: <20190821063236.19705-5-animesh.manna@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190821063236.19705-1-animesh.manna@intel.com> References: <20190821063236.19705-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 04/15] drm/i915/dsb: Added enum for reg write capability. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DSB can access specific register, To identify those register which can be written through DSB, enum reg_write_cap is added to hold the capability. Cc: Jani Nikula Cc: Rodrigo Vivi Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/i915_reg.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2abd199093c5..c4a17034d4dc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -178,11 +178,22 @@ */ #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) +/* + * Added enum to hold the capability for those registers which can be written + * through DSB. + */ +enum reg_write_cap { + MMIO_WRITE, + DSB_WRITE, + DSB_INDEX_WRITE +}; + typedef struct { u32 reg; + enum reg_write_cap cap; } i915_reg_t; -#define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) +#define _MMIO(r, ...) ((const i915_reg_t){ .reg = (r), ##__VA_ARGS__}) #define INVALID_MMIO_REG _MMIO(0)