From patchwork Wed Aug 21 06:32:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 11105565 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F1D841399 for ; Wed, 21 Aug 2019 06:40:25 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DA661206BA for ; Wed, 21 Aug 2019 06:40:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DA661206BA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C5A66E90D; Wed, 21 Aug 2019 06:40:25 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 457686E910 for ; Wed, 21 Aug 2019 06:40:16 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Aug 2019 23:40:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,411,1559545200"; d="scan'208";a="195935721" Received: from amanna.iind.intel.com ([10.223.74.216]) by fmsmga001.fm.intel.com with ESMTP; 20 Aug 2019 23:40:14 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Wed, 21 Aug 2019 12:02:27 +0530 Message-Id: <20190821063236.19705-8-animesh.manna@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190821063236.19705-1-animesh.manna@intel.com> References: <20190821063236.19705-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 07/15] drm/i915/dsb: Register definition of DSB registers. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Added key register definitions of DSB. dsb-ctrl register is required to enable dsb-engine. head-ptr register hold the head of buffer address from where the execution will start. Programming tail-ptr register is a trigger point to start execution. Cc: Uma Shankar Cc: Jani Nikula Cc: Rodrigo Vivi Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c4a17034d4dc..a1a9d09b6420 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -11550,4 +11550,19 @@ enum skl_power_gate { #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port)) +/* This register controls the Display State Buffer (DSB) engines. */ +#define _DSBSL_INSTANCE_BASE 0x70B00 +#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \ + (pipe) * 0x1000 + (id) * 100) +#define DSB_HEAD_PTR(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) +#define DSB_TAIL_PTR(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) +#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) +#define DSB_ENABLE (1 << 31) +#define DSB_BUFFER_REITERATE (1 << 29) +#define DSB_WAIT_FOR_VBLANK (1 << 28) +#define DSB_WAIT_FOR_LINE_IN_RANGE (1 << 27) +#define DSB_HALT (1 << 16) +#define DSB_NON_POSTED_ENABLE (1 << 8) +#define DSB_STATUS (1 << 0) + #endif /* _I915_REG_H_ */