| Message ID | 20190821215950.24223-1-manasi.d.navare@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dp: Fix DSC enable code to use cpu_transcoder instead of encoder->type | expand |
Op 21-08-2019 om 23:59 schreef Manasi Navare: > This patch fixes the intel_configure_pps_for_dsc_encoder() function to use > cpu_transcoder instead of encoder->type to select the correct DSC registers > that was wrongly used in the original patch for one DSC register isntance. > > Fixes: 7182414e2530 ("drm/i915/dp: Configure i915 Picture parameter Set > registers during DSC enabling") > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 598ddb60f9fb..d4fb7f16f9f6 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -547,7 +547,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | > DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); > DRM_INFO("PPS2 = 0x%08x\n", pps_val); > - if (encoder->type == INTEL_OUTPUT_EDP) { > + if (cpu_transcoder == TRANSCODER_EDP) { > I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); > /* > * If 2 VDSC instances are needed, configure PPS for second Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> I was already fixing this in the bigjoiner series, where encoder might be null entirely. :)
Thanks for the patch and review, pushed to dinq Manasi On Wed, Aug 21, 2019 at 02:59:50PM -0700, Manasi Navare wrote: > This patch fixes the intel_configure_pps_for_dsc_encoder() function to use > cpu_transcoder instead of encoder->type to select the correct DSC registers > that was wrongly used in the original patch for one DSC register isntance. > > Fixes: 7182414e2530 ("drm/i915/dp: Configure i915 Picture parameter Set > registers during DSC enabling") > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 598ddb60f9fb..d4fb7f16f9f6 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -547,7 +547,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | > DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); > DRM_INFO("PPS2 = 0x%08x\n", pps_val); > - if (encoder->type == INTEL_OUTPUT_EDP) { > + if (cpu_transcoder == TRANSCODER_EDP) { > I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); > /* > * If 2 VDSC instances are needed, configure PPS for second > -- > 2.19.1 >
On Thu, Aug 22, 2019 at 7:20 AM Manasi Navare <manasi.d.navare@intel.com> wrote: > > This patch fixes the intel_configure_pps_for_dsc_encoder() function to use > cpu_transcoder instead of encoder->type to select the correct DSC registers > that was wrongly used in the original patch for one DSC register isntance. > > Fixes: 7182414e2530 ("drm/i915/dp: Configure i915 Picture parameter Set > registers during DSC enabling") > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 598ddb60f9fb..d4fb7f16f9f6 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -547,7 +547,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | > DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); > DRM_INFO("PPS2 = 0x%08x\n", pps_val); > - if (encoder->type == INTEL_OUTPUT_EDP) { > + if (cpu_transcoder == TRANSCODER_EDP) { This will break tiger lake as there is no TRANSCODER_EDP there. Lucas De Marchi > I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); > /* > * If 2 VDSC instances are needed, configure PPS for second > -- > 2.19.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 598ddb60f9fb..d4fb7f16f9f6 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -547,7 +547,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); DRM_INFO("PPS2 = 0x%08x\n", pps_val); - if (encoder->type == INTEL_OUTPUT_EDP) { + if (cpu_transcoder == TRANSCODER_EDP) { I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); /* * If 2 VDSC instances are needed, configure PPS for second
This patch fixes the intel_configure_pps_for_dsc_encoder() function to use cpu_transcoder instead of encoder->type to select the correct DSC registers that was wrongly used in the original patch for one DSC register isntance. Fixes: 7182414e2530 ("drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling") Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)