From patchwork Thu Aug 22 18:32:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Summers, Stuart" X-Patchwork-Id: 11109761 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 221441395 for ; Thu, 22 Aug 2019 18:31:29 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0B65E206BB for ; Thu, 22 Aug 2019 18:31:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0B65E206BB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D26D56EA14; Thu, 22 Aug 2019 18:31:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6E318892D5 for ; Thu, 22 Aug 2019 18:31:21 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Aug 2019 11:31:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,417,1559545200"; d="scan'208";a="354376286" Received: from jssummer-xeon.ra.intel.com ([10.23.184.90]) by orsmga005.jf.intel.com with ESMTP; 22 Aug 2019 11:31:20 -0700 From: Stuart Summers To: intel-gfx@lists.freedesktop.org Date: Thu, 22 Aug 2019 11:32:09 -0700 Message-Id: <20190822183213.132380-8-stuart.summers@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190822183213.132380-1-stuart.summers@intel.com> References: <20190822183213.132380-1-stuart.summers@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a subslice stride calculation when setting subslices. This aligns more closely with the userspace expectation of the subslice mask structure. v2: Use local variable for subslice_mask on HSW and clean up a few other subslice_mask local variable changes v3: Add GEM_BUG_ON for ss_stride to prevent array overflow (Chris) Split main set function and refactors in intel_device_info.c into separate patches (Chris) v4: Reduce ss_stride size check when setting subslices per slice based on actual expected max stride (Chris) Move that GEM_BUG_ON check for the ss_stride out to the patch which adds the ss_stride Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/gt/intel_sseu.c | 8 ++++++-- drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index 3a5db0dbac72..a0d32270248c 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -33,9 +33,13 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu) } void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, - u8 ss_mask) + u32 ss_mask) { - sseu->subslice_mask[slice] = ss_mask; + int i, offset = slice * sseu->ss_stride; + + for (i = 0; i < sseu->ss_stride; i++) + sseu->subslice_mask[offset + i] = + (ss_mask >> (BITS_PER_BYTE * i)) & 0xff; } unsigned int diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h index 7f600f50dedb..73a9064291a2 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.h +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h @@ -79,7 +79,7 @@ unsigned int intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice); void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, - u8 ss_mask); + u32 ss_mask); u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, const struct intel_sseu *req_sseu);