From patchwork Wed Sep 11 10:19:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 11140855 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E253F1599 for ; Wed, 11 Sep 2019 10:20:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C9DB1207FC for ; Wed, 11 Sep 2019 10:20:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C9DB1207FC Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=chris-wilson.co.uk Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 135CB6E220; Wed, 11 Sep 2019 10:20:09 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id 080466E220 for ; Wed, 11 Sep 2019 10:20:07 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 18449238-1500050 for multiple; Wed, 11 Sep 2019 11:20:00 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Wed, 11 Sep 2019 11:19:59 +0100 Message-Id: <20190911101959.13793-1-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190910073931.GY7482@intel.com> References: <20190910073931.GY7482@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2] drm/i915/gt: Allow clobbering gpu resets if the display is off X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" If the display is inactive, we need not worry about the gpu reset clobbering the display! To prevent the display changing state between us checking the active state and doing the hard reset, we introduce the lightweight reset lock to the atomic commit for the affected (legacy) platforms. Testcase: igt/gem_eio/kms Signed-off-by: Chris Wilson Cc: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_reset.c | 18 +++++++++++++++++- 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 4ee750fa3ef0..a92487d8f4cf 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13986,6 +13986,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) struct intel_crtc *crtc; u64 put_domains[I915_MAX_PIPES] = {}; intel_wakeref_t wakeref = 0; + int srcu; int i; intel_atomic_commit_fence_wait(state); @@ -14005,6 +14006,12 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) } } + /* Prevent starting a GPU reset while we change global display state */ + srcu = -ENODEV; + if (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display) + /* only fails if interrupted */ + srcu = intel_gt_reset_trylock(&dev_priv->gt); + intel_commit_modeset_disables(state); /* FIXME: Eventually get rid of our crtc->config pointer */ @@ -14049,6 +14056,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) /* Now enable the clocks, plane, pipe, and connectors that we set up. */ dev_priv->display.commit_modeset_enables(state); + + if (srcu > 0) + intel_gt_reset_unlock(&dev_priv->gt, srcu); + if (state->modeset) { intel_encoders_update_complete(state); diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index d8b1498d7ab7..df4a86bdb6f6 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -7,6 +7,7 @@ #include #include +#include "display/intel_display.h" #include "display/intel_display_types.h" #include "display/intel_overlay.h" @@ -729,6 +730,21 @@ static void nop_submit_request(struct i915_request *request) intel_engine_queue_breadcrumbs(engine); } +static bool reset_clobbers_display(struct drm_i915_private *i915) +{ + struct intel_crtc *crtc; + + if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) + return false; + + for_each_intel_crtc(&i915->drm, crtc) { + if (crtc->active) + return true; + } + + return false; +} + static void __intel_gt_set_wedged(struct intel_gt *gt) { struct intel_engine_cs *engine; @@ -755,7 +771,7 @@ static void __intel_gt_set_wedged(struct intel_gt *gt) awake = reset_prepare(gt); /* Even if the GPU reset fails, it should still stop the engines */ - if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) + if (!reset_clobbers_display(gt->i915)) __intel_gt_reset(gt, ALL_ENGINES); for_each_engine(engine, gt->i915, id)