diff mbox series

[02/14] drm/i915/tgl: TC helper function to return pin mapping

Message ID 20190913223251.354877-3-jose.souza@intel.com (mailing list archive)
State New, archived
Headers show
Series TGL TC enabling | expand

Commit Message

Souza, Jose Sept. 13, 2019, 10:32 p.m. UTC 
From: "Taylor, Clinton A" <clinton.a.taylor@intel.com>

Add a helper function to return pin map for use during dkl phy
DP_MODE settings, PORT_TX_DFLEXPA1 exist on ICL but we don't need it.

The user of this function will come in future TC patches.

Signed-off-by: Taylor, Clinton A <clinton.a.taylor@intel.com>
---
 drivers/gpu/drm/i915/display/intel_tc.c | 16 ++++++++++++++++
 drivers/gpu/drm/i915/display/intel_tc.h |  1 +
 drivers/gpu/drm/i915/i915_reg.h         |  5 +++++
 3 files changed, 22 insertions(+)

Comments

Lucas De Marchi Sept. 14, 2019, 5:54 a.m. UTC | #1 
On Fri, Sep 13, 2019 at 3:33 PM José Roberto de Souza
<jose.souza@intel.com> wrote:
>
> From: "Taylor, Clinton A" <clinton.a.taylor@intel.com>
>
> Add a helper function to return pin map for use during dkl phy
> DP_MODE settings, PORT_TX_DFLEXPA1 exist on ICL but we don't need it.
>
> The user of this function will come in future TC patches.

It's actually harder to review if the function is out of the context
of those patches. Will it really be needed outside of intel_tc.c ?

>
> Signed-off-by: Taylor, Clinton A <clinton.a.taylor@intel.com>

you need your s-o-b too if you are sending this patch.

> ---
>  drivers/gpu/drm/i915/display/intel_tc.c | 16 ++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_tc.h |  1 +
>  drivers/gpu/drm/i915/i915_reg.h         |  5 +++++
>  3 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 85743a43bee2..3a7302e360cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -61,6 +61,22 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
>                DP_LANE_ASSIGNMENT_SHIFT(tc_port);
>  }
>
> +u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
> +{
> +       struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +       enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
> +       struct intel_uncore *uncore = &i915->uncore;
> +       u32 pin_mask;
> +
> +       pin_mask = intel_uncore_read(uncore,
> +                                    PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
> +
> +       WARN_ON(pin_mask == 0xffffffff);
> +
> +       return (pin_mask & DP_PIN_ASSIGNMENT_MASK(tc_port)) >>
> +              DP_PIN_ASSIGNMENT_SHIFT(tc_port);
> +}
> +
>  int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
>  {
>         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
> index 783d75531435..463f1b3c836f 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.h
> +++ b/drivers/gpu/drm/i915/display/intel_tc.h
> @@ -13,6 +13,7 @@ struct intel_digital_port;
>
>  bool intel_tc_port_connected(struct intel_digital_port *dig_port);
>  u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
> +u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
>  int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
>  void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
>                                       int required_lanes);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bf37ecebc82f..16d5548adb84 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11683,4 +11683,9 @@ enum skl_power_gate {
>  #define PORT_TX_DFLEXDPCSSS(fia)               _MMIO_FIA((fia), 0x00894)
>  #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)         (1 << (tc_port))
>
> +#define PORT_TX_DFLEXPA1(fia)                  _MMIO_FIA((fia), 0x00880)
> +#define   DP_PIN_ASSIGNMENT_SHIFT(tc_port)             ((tc_port) * 4)
> +#define   DP_PIN_ASSIGNMENT_MASK(tc_port)              (0xf << ((tc_port) * 4))

Use DP_PIN_ASSIGNMENT_SHIFT() here

> +#define   DP_PIN_ASSIGNMENT(tc_port, x)        ((x) << ((tc_port) * 4))

ditto.

Lucas De Marchi

> +
>  #endif /* _I915_REG_H_ */
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Souza, Jose Sept. 17, 2019, 9:15 p.m. UTC | #2 
On Fri, 2019-09-13 at 22:54 -0700, Lucas De Marchi wrote:
> On Fri, Sep 13, 2019 at 3:33 PM José Roberto de Souza
> <jose.souza@intel.com> wrote:
> > From: "Taylor, Clinton A" <clinton.a.taylor@intel.com>
> > 
> > Add a helper function to return pin map for use during dkl phy
> > DP_MODE settings, PORT_TX_DFLEXPA1 exist on ICL but we don't need
> > it.
> > 
> > The user of this function will come in future TC patches.
> 
> It's actually harder to review if the function is out of the context
> of those patches. Will it really be needed outside of intel_tc.c ?

It is used in intel_ddi.c, the user is added in "drm/i915/tgl: Add dkl
phy programming sequences" I guess I can move this patch right before
that one.

> 
> > Signed-off-by: Taylor, Clinton A <clinton.a.taylor@intel.com>
> 
> you need your s-o-b too if you are sending this patch.
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_tc.c | 16 ++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_tc.h |  1 +
> >  drivers/gpu/drm/i915/i915_reg.h         |  5 +++++
> >  3 files changed, 22 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> > b/drivers/gpu/drm/i915/display/intel_tc.c
> > index 85743a43bee2..3a7302e360cc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -61,6 +61,22 @@ u32 intel_tc_port_get_lane_mask(struct
> > intel_digital_port *dig_port)
> >                DP_LANE_ASSIGNMENT_SHIFT(tc_port);
> >  }
> > 
> > +u32 intel_tc_port_get_pin_assignment_mask(struct
> > intel_digital_port *dig_port)
> > +{
> > +       struct drm_i915_private *i915 = to_i915(dig_port-
> > >base.base.dev);
> > +       enum tc_port tc_port = intel_port_to_tc(i915, dig_port-
> > >base.port);
> > +       struct intel_uncore *uncore = &i915->uncore;
> > +       u32 pin_mask;
> > +
> > +       pin_mask = intel_uncore_read(uncore,
> > +                                    PORT_TX_DFLEXPA1(dig_port-
> > >tc_phy_fia));
> > +
> > +       WARN_ON(pin_mask == 0xffffffff);
> > +
> > +       return (pin_mask & DP_PIN_ASSIGNMENT_MASK(tc_port)) >>
> > +              DP_PIN_ASSIGNMENT_SHIFT(tc_port);
> > +}
> > +
> >  int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> > *dig_port)
> >  {
> >         struct drm_i915_private *i915 = to_i915(dig_port-
> > >base.base.dev);
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.h
> > b/drivers/gpu/drm/i915/display/intel_tc.h
> > index 783d75531435..463f1b3c836f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.h
> > @@ -13,6 +13,7 @@ struct intel_digital_port;
> > 
> >  bool intel_tc_port_connected(struct intel_digital_port *dig_port);
> >  u32 intel_tc_port_get_lane_mask(struct intel_digital_port
> > *dig_port);
> > +u32 intel_tc_port_get_pin_assignment_mask(struct
> > intel_digital_port *dig_port);
> >  int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> > *dig_port);
> >  void intel_tc_port_set_fia_lane_count(struct intel_digital_port
> > *dig_port,
> >                                       int required_lanes);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index bf37ecebc82f..16d5548adb84 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -11683,4 +11683,9 @@ enum skl_power_gate {
> >  #define PORT_TX_DFLEXDPCSSS(fia)               _MMIO_FIA((fia),
> > 0x00894)
> >  #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)         (1 <<
> > (tc_port))
> > 
> > +#define PORT_TX_DFLEXPA1(fia)                  _MMIO_FIA((fia),
> > 0x00880)
> > +#define   DP_PIN_ASSIGNMENT_SHIFT(tc_port)             ((tc_port)
> > * 4)
> > +#define   DP_PIN_ASSIGNMENT_MASK(tc_port)              (0xf <<
> > ((tc_port) * 4))
> 
> Use DP_PIN_ASSIGNMENT_SHIFT() here
> 
> > +#define   DP_PIN_ASSIGNMENT(tc_port, x)        ((x) << ((tc_port)
> > * 4))
> 
> ditto.
> 
> Lucas De Marchi
> 
> > +
> >  #endif /* _I915_REG_H_ */
> > --
> > 2.23.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 85743a43bee2..3a7302e360cc 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -61,6 +61,22 @@  u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
 	       DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 }
 
+u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+	struct intel_uncore *uncore = &i915->uncore;
+	u32 pin_mask;
+
+	pin_mask = intel_uncore_read(uncore,
+				     PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
+
+	WARN_ON(pin_mask == 0xffffffff);
+
+	return (pin_mask & DP_PIN_ASSIGNMENT_MASK(tc_port)) >>
+	       DP_PIN_ASSIGNMENT_SHIFT(tc_port);
+}
+
 int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
index 783d75531435..463f1b3c836f 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -13,6 +13,7 @@  struct intel_digital_port;
 
 bool intel_tc_port_connected(struct intel_digital_port *dig_port);
 u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
+u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
 int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
 				      int required_lanes);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..16d5548adb84 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11683,4 +11683,9 @@  enum skl_power_gate {
 #define PORT_TX_DFLEXDPCSSS(fia)		_MMIO_FIA((fia), 0x00894)
 #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)		(1 << (tc_port))
 
+#define PORT_TX_DFLEXPA1(fia)			_MMIO_FIA((fia), 0x00880)
+#define   DP_PIN_ASSIGNMENT_SHIFT(tc_port)		((tc_port) * 4)
+#define   DP_PIN_ASSIGNMENT_MASK(tc_port)		(0xf << ((tc_port) * 4))
+#define   DP_PIN_ASSIGNMENT(tc_port, x)	((x) << ((tc_port) * 4))
+
 #endif /* _I915_REG_H_ */