From patchwork Fri Sep 20 10:44:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 11154217 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6BD0B1747 for ; Fri, 20 Sep 2019 10:46:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 46EFA207FC for ; Fri, 20 Sep 2019 10:46:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 46EFA207FC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 76D736F98E; Fri, 20 Sep 2019 10:46:30 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0E7046F98E for ; Fri, 20 Sep 2019 10:46:29 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Sep 2019 03:46:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,528,1559545200"; d="scan'208";a="387574494" Received: from slisovsk-lenovo-ideapad-720s-13ikb.fi.intel.com ([10.237.72.89]) by fmsmga005.fm.intel.com with ESMTP; 20 Sep 2019 03:46:25 -0700 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Date: Fri, 20 Sep 2019 13:44:13 +0300 Message-Id: <20190920104413.21410-1-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.17.1 Subject: [Intel-gfx] [PATCH v2] drm/i915: Restrict qgv points which don't have enough bandwidth. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, martin.peres@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" According to BSpec 53998, we should try to restrict qgv points, which can't provide enough bandwidth for desired display configuration. Currently we are just comparing against all of those and take minimum(worst case). v2: Fixed wrong PCode reply mask, removed hardcoded values. Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_bw.c | 58 +++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 3 ++ 2 files changed, 58 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index cd58e47ab7b2..7653cbdb0ee4 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -90,6 +90,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, return 0; } +static int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, u32 points_mask) +{ + int ret; + + /* bspec says to keep retrying for at least 1 ms */ + ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG, + points_mask, + GEN11_PCODE_POINTS_RESTRICTED_MASK, + GEN11_PCODE_POINTS_RESTRICTED, + 1); + + if (ret < 0) { + DRM_ERROR("Failed to disable qgv points (%d)\n", ret); + return ret; + } + + return 0; +} + + static int icl_get_qgv_points(struct drm_i915_private *dev_priv, struct intel_qgv_info *qi) { @@ -354,7 +374,9 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) unsigned int data_rate, max_data_rate; unsigned int num_active_planes; struct intel_crtc *crtc; - int i; + int i, ret; + struct intel_qgv_info qi = {}; + u32 points_mask = 0; /* FIXME earlier gens need some checks too */ if (INTEL_GEN(dev_priv) < 11) @@ -398,10 +420,40 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) data_rate = intel_bw_data_rate(dev_priv, bw_state); num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state); - max_data_rate = intel_max_data_rate(dev_priv, num_active_planes); - data_rate = DIV_ROUND_UP(data_rate, 1000); + ret = icl_get_qgv_points(dev_priv, &qi); + if (ret < 0) { + goto fallback; + } + + for (i = 0; i < qi.num_points; i++) { + max_data_rate = icl_max_bw(dev_priv, num_active_planes, i); + if (max_data_rate < data_rate) { + DRM_DEBUG_KMS("QGV point %d: max bw %d required %d restricted\n", + i, max_data_rate, data_rate); + points_mask |= 1 << i; + } else + DRM_DEBUG_KMS("QGV point %d: max bw %d required %d unrestricted\n", + i, max_data_rate, data_rate); + } + + if (points_mask >= ((1 << qi.num_points) - 1)) { + DRM_DEBUG_KMS("Could not find any suitable QGV points\n"); + return -EINVAL; + } + + ret = icl_pcode_restrict_qgv_points(dev_priv, points_mask); + if (ret < 0) { + DRM_DEBUG_KMS("Could not restrict required gqv points(%d)\n", ret); + goto fallback; + } + + return 0; + +fallback: + max_data_rate = intel_max_data_rate(dev_priv, num_active_planes); + if (data_rate > max_data_rate) { DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n", data_rate, max_data_rate, num_active_planes); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bf37ecebc82f..fe327fee8781 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8845,6 +8845,7 @@ enum { #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) +#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe #define GEN6_PCODE_READ_D_COMP 0x10 #define GEN6_PCODE_WRITE_D_COMP 0x11 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 @@ -8856,6 +8857,8 @@ enum { #define GEN9_SAGV_DISABLE 0x0 #define GEN9_SAGV_IS_DISABLED 0x1 #define GEN9_SAGV_ENABLE 0x3 +#define GEN11_PCODE_POINTS_RESTRICTED 0x0 +#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1 #define GEN6_PCODE_DATA _MMIO(0x138128) #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16