From patchwork Wed Sep 25 20:33:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: James Ausmus X-Patchwork-Id: 11161349 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BD9DA13B1 for ; Wed, 25 Sep 2019 20:33:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A5A7B21D79 for ; Wed, 25 Sep 2019 20:33:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A5A7B21D79 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1E4BD6FB5D; Wed, 25 Sep 2019 20:33:36 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 28C916FB63 for ; Wed, 25 Sep 2019 20:33:28 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Sep 2019 13:33:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,549,1559545200"; d="scan'208";a="219110792" Received: from jausmus-gentoo-dev6.jf.intel.com (HELO jausmus-gentoo-dev6) ([10.54.75.43]) by fmsmga002.fm.intel.com with SMTP; 25 Sep 2019 13:33:26 -0700 Received: by jausmus-gentoo-dev6 (sSMTP sendmail emulation); Wed, 25 Sep 2019 13:34:04 -0700 From: James Ausmus To: intel-gfx@lists.freedesktop.org Date: Wed, 25 Sep 2019 13:33:52 -0700 Message-Id: <20190925203352.9827-4-james.ausmus@intel.com> X-Mailer: git-send-email 2.22.1 In-Reply-To: <20190925203352.9827-1-james.ausmus@intel.com> References: <20190925203352.9827-1-james.ausmus@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/3] drm/i915/tgl: Remove single pipe restriction from SAGV X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For Gen12, BSpec no longer tells us to disable SAGV when > 1 pipe is active. Update intel_can_enable_sagv to allow this, and loop through all active planes on all active crtcs to check against the interlaced and latency restrictions. BSpec: 49325 Cc: Ville Syrjälä Cc: Stanislav Lisovskiy Cc: Lucas De Marchi Signed-off-by: James Ausmus --- drivers/gpu/drm/i915/intel_pm.c | 63 +++++++++++++++++---------------- 1 file changed, 32 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ca2bec09edb5..cb50c697a6b8 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3775,7 +3775,6 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state) struct intel_crtc *crtc; struct intel_plane *plane; struct intel_crtc_state *crtc_state; - enum pipe pipe; int level, latency; int sagv_block_time_us; @@ -3791,47 +3790,49 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state) return true; /* - * SKL+ workaround: bspec recommends we disable SAGV when we have + * SKL-ICL workaround: bspec recommends we disable SAGV when we have * more then one pipe enabled */ - if (hweight8(state->active_pipes) > 1) + if (INTEL_GEN(dev_priv) < 12 && hweight8(state->active_pipes) > 1) return false; - /* Since we're now guaranteed to only have one active CRTC... */ - pipe = ffs(state->active_pipes) - 1; - crtc = intel_get_crtc_for_pipe(dev_priv, pipe); - crtc_state = to_intel_crtc_state(crtc->base.state); + for_each_intel_crtc(&dev_priv->drm, crtc) { + crtc_state = to_intel_crtc_state(crtc->base.state); + if (!crtc_state->base.active) + continue; - if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) - return false; + if (crtc->base.state->adjusted_mode.flags & + DRM_MODE_FLAG_INTERLACE) + return false; - for_each_intel_plane_on_crtc(dev, crtc, plane) { - struct skl_plane_wm *wm = - &crtc_state->wm.skl.optimal.planes[plane->id]; + for_each_intel_plane_on_crtc(dev, crtc, plane) { + struct skl_plane_wm *wm = + &crtc_state->wm.skl.optimal.planes[plane->id]; - /* Skip this plane if it's not enabled */ - if (!wm->wm[0].plane_en) - continue; + /* Skip this plane if it's not enabled */ + if (!wm->wm[0].plane_en) + continue; - /* Find the highest enabled wm level for this plane */ - for (level = ilk_wm_max_level(dev_priv); - !wm->wm[level].plane_en; --level) - { } + /* Find the highest enabled wm level for this plane */ + for (level = ilk_wm_max_level(dev_priv); + !wm->wm[level].plane_en; --level) + { } - latency = dev_priv->wm.skl_latency[level]; + latency = dev_priv->wm.skl_latency[level]; - if (skl_needs_memory_bw_wa(dev_priv) && - plane->base.state->fb->modifier == - I915_FORMAT_MOD_X_TILED) - latency += 15; + if (skl_needs_memory_bw_wa(dev_priv) && + plane->base.state->fb->modifier == + I915_FORMAT_MOD_X_TILED) + latency += 15; - /* - * If any of the planes on this pipe don't enable wm levels that - * incur memory latencies higher than sagv_block_time_us we - * can't enable SAGV. - */ - if (latency < sagv_block_time_us) - return false; + /* + * If any of the planes on this pipe don't enable wm + * levels that incur memory latencies higher than + * sagv_block_time_us we can't enable SAGV. + */ + if (latency < sagv_block_time_us) + return false; + } } return true;