From patchwork Thu Oct 3 15:06:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Animesh Manna X-Patchwork-Id: 11172777 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A714D13B1 for ; Thu, 3 Oct 2019 15:15:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8EE5B215EA for ; Thu, 3 Oct 2019 15:15:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8EE5B215EA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 002776EA13; Thu, 3 Oct 2019 15:15:56 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id D68906EA14 for ; Thu, 3 Oct 2019 15:15:55 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Oct 2019 08:15:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,252,1566889200"; d="scan'208";a="391976333" Received: from amanna.iind.intel.com ([10.223.74.216]) by fmsmga005.fm.intel.com with ESMTP; 03 Oct 2019 08:15:53 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Thu, 3 Oct 2019 20:36:53 +0530 Message-Id: <20191003150653.15881-7-animesh.manna@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20191003150653.15881-1-animesh.manna@intel.com> References: <20191003150653.15881-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 6/6] drm/i915/dp: Program vswing, pre-emphasis, test-pattern X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This patch process phy compliance request by programming requested vswing, pre-emphasis and test pattern. Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_dp.c | 62 +++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 93b1ce80c174..dd4c3a81c11d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4817,14 +4817,76 @@ static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) } } +static void +intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) +{ + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = intel_dig_port->base.base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + enum port port = intel_dig_port->base.port; + u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value; + + ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port)); + dp_tp_ctl_value = I915_READ(DP_TP_CTL(port)); + trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port)); + + ddi_buf_ctl_value &= ~(DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH_MASK); + dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; + trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | + DDI_PORT_WIDTH_MASK); + + I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value); + I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value); + I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value); +} + +static void +intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt) +{ + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = intel_dig_port->base.base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + enum port port = intel_dig_port->base.port; + u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value; + + ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port)); + dp_tp_ctl_value = I915_READ(DP_TP_CTL(port)); + trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port)); + + ddi_buf_ctl_value |= DDI_BUF_CTL_ENABLE | + DDI_PORT_WIDTH(lane_cnt); + dp_tp_ctl_value |= DP_TP_CTL_ENABLE; + trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | + DDI_PORT_WIDTH(lane_cnt); + + I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value); + I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value); + I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value); +} + static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) { u8 test_result = DP_TEST_NAK; + struct drm_dp_phy_test_params *data = + &intel_dp->compliance.test_data.phytest; test_result = intel_dp_prepare_phytest(intel_dp); if (test_result != DP_TEST_ACK) DRM_ERROR("Phy test preparation failed\n"); + intel_dp_autotest_phy_ddi_disable(intel_dp); + + intel_dp_set_signal_levels(intel_dp); + + intel_dp_phy_pattern_update(intel_dp); + + intel_dp_autotest_phy_ddi_enable(intel_dp, data->link.num_lanes); + + drm_dp_set_phy_test_pattern(&intel_dp->aux, data); + + /* Set test active flag here so userspace doesn't interrupt things */ + intel_dp->compliance.test_active = 1; + return test_result; }