| Message ID | 20191011002618.3087-1-vivek.kasireddy@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/ehl: Port C's hotplug interrupt is associated with TC1 bits | expand |
On Thu, 2019-10-10 at 17:26 -0700, Vivek Kasireddy wrote: > On some platforms that have the MCC PCH, Port C's hotplug interrupt Some? > bits are mapped to TC1 bits. > > Suggested-by: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ > drivers/gpu/drm/i915/i915_irq.c | 8 ++++---- > 2 files changed, 7 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 0e45c61d7331..6594f2af1257 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5282,6 +5282,9 @@ static bool icl_combo_port_connected(struct > drm_i915_private *dev_priv, > { > enum port port = intel_dig_port->base.port; > > + if (HAS_PCH_MCC(dev_priv) && port == PORT_C) > + return I915_READ(SDEISR) & > SDE_TC_HOTPLUG_ICP(PORT_TC1); > + > return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port); > } > > diff --git a/drivers/gpu/drm/i915/i915_irq.c > b/drivers/gpu/drm/i915/i915_irq.c > index 3af7f7914c40..a7c968b01af3 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2249,8 +2249,8 @@ static void icp_irq_handler(struct > drm_i915_private *dev_priv, u32 pch_iir) > tc_port_hotplug_long_detect = > tgp_tc_port_hotplug_long_detect; > pins = hpd_tgp; > } else if (HAS_PCH_MCC(dev_priv)) { > - ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; > - tc_hotplug_trigger = 0; > + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; > + tc_hotplug_trigger = pch_iir & > SDE_TC_HOTPLUG_ICP(PORT_TC1); > pins = hpd_icp; > } else { > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; > @@ -3377,8 +3377,8 @@ static void icp_hpd_irq_setup(struct > drm_i915_private *dev_priv, > static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) > { > icp_hpd_irq_setup(dev_priv, > - SDE_DDI_MASK_TGP, 0, > - TGP_DDI_HPD_ENABLE_MASK, 0, > + SDE_DDI_MASK_ICP, > SDE_TC_HOTPLUG_ICP(PORT_TC1), > + ICP_DDI_HPD_ENABLE_MASK, > ICP_TC_HPD_ENABLE(PORT_TC1), > hpd_icp); > } >
On Thu, Oct 10, 2019 at 05:26:18PM -0700, Vivek Kasireddy wrote: > On some platforms that have the MCC PCH, Port C's hotplug interrupt > bits are mapped to TC1 bits. > > Suggested-by: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com> As Jose pointed out, the "some" in the message here isn't correct; all MCC platforms should behave this way, and the other PCH we were working with previously turned out to be something different (not actually MCC); I'll send a separate patch to deal with that other PCH in the next day or two. Aside from that, Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Applied to dinq (with a tweaked commit message). Thanks for the patch. Matt > --- > drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ > drivers/gpu/drm/i915/i915_irq.c | 8 ++++---- > 2 files changed, 7 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 0e45c61d7331..6594f2af1257 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5282,6 +5282,9 @@ static bool icl_combo_port_connected(struct drm_i915_private *dev_priv, > { > enum port port = intel_dig_port->base.port; > > + if (HAS_PCH_MCC(dev_priv) && port == PORT_C) > + return I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1); > + > return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port); > } > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 3af7f7914c40..a7c968b01af3 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2249,8 +2249,8 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) > tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect; > pins = hpd_tgp; > } else if (HAS_PCH_MCC(dev_priv)) { > - ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; > - tc_hotplug_trigger = 0; > + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; > + tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1); > pins = hpd_icp; > } else { > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; > @@ -3377,8 +3377,8 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, > static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) > { > icp_hpd_irq_setup(dev_priv, > - SDE_DDI_MASK_TGP, 0, > - TGP_DDI_HPD_ENABLE_MASK, 0, > + SDE_DDI_MASK_ICP, SDE_TC_HOTPLUG_ICP(PORT_TC1), > + ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1), > hpd_icp); > } > > -- > 2.21.0 >
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0e45c61d7331..6594f2af1257 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5282,6 +5282,9 @@ static bool icl_combo_port_connected(struct drm_i915_private *dev_priv, { enum port port = intel_dig_port->base.port; + if (HAS_PCH_MCC(dev_priv) && port == PORT_C) + return I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1); + return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port); } diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 3af7f7914c40..a7c968b01af3 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2249,8 +2249,8 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect; pins = hpd_tgp; } else if (HAS_PCH_MCC(dev_priv)) { - ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; - tc_hotplug_trigger = 0; + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; + tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1); pins = hpd_icp; } else { ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; @@ -3377,8 +3377,8 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) { icp_hpd_irq_setup(dev_priv, - SDE_DDI_MASK_TGP, 0, - TGP_DDI_HPD_ENABLE_MASK, 0, + SDE_DDI_MASK_ICP, SDE_TC_HOTPLUG_ICP(PORT_TC1), + ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1), hpd_icp); }
On some platforms that have the MCC PCH, Port C's hotplug interrupt bits are mapped to TC1 bits. Suggested-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ drivers/gpu/drm/i915/i915_irq.c | 8 ++++---- 2 files changed, 7 insertions(+), 4 deletions(-)