| Message ID | 20191011133911.18621-3-mika.kuoppala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/3] drm/i915/tgl: Include ro parts of l3 to invalidate | expand |
Quoting Mika Kuoppala (2019-10-11 14:39:11) > In order to ensure constant caches are invalidated > properly with a0, we need extra hdc flush after invalidation. > > References: HSDES#1604544889 > Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index 967e5b2e5e80..8db86772d8d4 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -3236,6 +3236,24 @@ static int gen12_emit_flush_render(struct i915_request *request, > > *cs++ = preparser_disable(false); > intel_ring_advance(request, cs); > + > + /* > + * Workaround constant cache invalidation issue > + * for tgl:a0, #1604544889 Do we have IS_TGL_REVID() yet? They should act as a reminder to remove them later. > + */ > + flags = 0; > + flags |= PIPE_CONTROL_CS_STALL; > + flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH; > + > + flags |= PIPE_CONTROL_STORE_DATA_INDEX; > + flags |= PIPE_CONTROL_QW_WRITE; Acked-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 967e5b2e5e80..8db86772d8d4 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3236,6 +3236,24 @@ static int gen12_emit_flush_render(struct i915_request *request, *cs++ = preparser_disable(false); intel_ring_advance(request, cs); + + /* + * Workaround constant cache invalidation issue + * for tgl:a0, #1604544889 + */ + flags = 0; + flags |= PIPE_CONTROL_CS_STALL; + flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH; + + flags |= PIPE_CONTROL_STORE_DATA_INDEX; + flags |= PIPE_CONTROL_QW_WRITE; + + cs = intel_ring_begin(request, 6); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); + intel_ring_advance(request, cs); } return 0;
In order to ensure constant caches are invalidated properly with a0, we need extra hdc flush after invalidation. References: HSDES#1604544889 Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)