| Message ID | 20191014224341.12923-1-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] drm/i915: Introduce Jasper Lake PCH | expand |
On Mon, 14 Oct 2019 15:43:41 -0700 Matt Roper <matthew.d.roper@intel.com> wrote: > The Jasper Lake PCH follows ICP/TGP's south display behavior and is > identical to MCC graphics-wise except that it does not use the unusual > (port C -> TC1) pin mapping that MCC does. > > Also, it turns out the extra PCH ID that we had previously thought > was a form of MCC is actually a second ID for JSP (i.e., port C uses > the port C pins instead of the TC1 pins). > > v2: > - Also update the port masks (not just the pin table) in > mcc_hpd_irq_setup. (Vivek) > > Cc: José Roberto de Souza <jose.souza@intel.com> > Cc: James Ausmus <james.ausmus@intel.com> > Cc: Vivek Kasireddy <vivek.kasireddy@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 31 +++++++++++++++++++++++++------ > drivers/gpu/drm/i915/intel_pch.c | 6 +++++- > drivers/gpu/drm/i915/intel_pch.h | 5 ++++- > 3 files changed, 34 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c > b/drivers/gpu/drm/i915/i915_irq.c index d20ca02d3166..81e9ed48ce9f > 100644 --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2248,11 +2248,18 @@ static void icp_irq_handler(struct > drm_i915_private *dev_priv, u32 pch_iir) tc_hotplug_trigger = pch_iir > & SDE_TC_MASK_TGP; tc_port_hotplug_long_detect = > tgp_tc_port_hotplug_long_detect; pins = hpd_tgp; > + } else if (HAS_PCH_JSP(dev_priv)) { > + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; > + tc_hotplug_trigger = 0; > + pins = hpd_tgp; > } else if (HAS_PCH_MCC(dev_priv)) { > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; > tc_hotplug_trigger = pch_iir & > SDE_TC_HOTPLUG_ICP(PORT_TC1); pins = hpd_icp; > } else { > + WARN(!HAS_PCH_ICP(dev_priv), > + "Unrecognized PCH type 0x%x\n", > INTEL_PCH_TYPE(dev_priv)); + > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; > tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; > tc_port_hotplug_long_detect = > icp_tc_port_hotplug_long_detect; @@ -3373,15 +3380,27 @@ static void > icp_hpd_irq_setup(struct drm_i915_private *dev_priv, } > > /* > - * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only > the > + * EHL/JSL don't need most of gen11_hpd_irq_setup, they're handling > only the > * equivalent of SDE. > + * > + * Note that MCC and JSP have different port C pin mappings, hence > the use of > + * ICP's masks & tables (hpd C on TC1) vs TGP's masks & tables (hpd > C on DDIC) > + * depending on platform. > */ > static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) > { > - icp_hpd_irq_setup(dev_priv, > - SDE_DDI_MASK_ICP, > SDE_TC_HOTPLUG_ICP(PORT_TC1), > - ICP_DDI_HPD_ENABLE_MASK, > ICP_TC_HPD_ENABLE(PORT_TC1), > - hpd_icp); > + if (HAS_PCH_JSP(dev_priv)) > + icp_hpd_irq_setup(dev_priv, > + SDE_DDI_MASK_TGP, 0, > + TGP_DDI_HPD_ENABLE_MASK, 0, > + hpd_tgp); > + else > + icp_hpd_irq_setup(dev_priv, > + SDE_DDI_MASK_ICP, > + SDE_TC_HOTPLUG_ICP(PORT_TC1), > + ICP_DDI_HPD_ENABLE_MASK, > + ICP_TC_HPD_ENABLE(PORT_TC1), > + hpd_icp); Although MCC and JSL PCH are similar, wouldn't it be a bit cleaner if we had a separate function for JSP? Something like jsp_hpd_irq_setup()... Regarldess, this patch is Reviewed-by: Vivek Kasireddy <vivek.kasireddy@intel.com> Thanks, Vivek > } > > static void gen11_hpd_detection_setup(struct drm_i915_private > *dev_priv) @@ -4315,7 +4334,7 @@ void intel_irq_init(struct > drm_i915_private *dev_priv) if (I915_HAS_HOTPLUG(dev_priv)) > dev_priv->display.hpd_irq_setup = > i915_hpd_irq_setup; } else { > - if (HAS_PCH_MCC(dev_priv)) > + if (HAS_PCH_MCC(dev_priv) || HAS_PCH_JSP(dev_priv)) > dev_priv->display.hpd_irq_setup = > mcc_hpd_irq_setup; else if (INTEL_GEN(dev_priv) >= 11) > dev_priv->display.hpd_irq_setup = > gen11_hpd_irq_setup; diff --git a/drivers/gpu/drm/i915/intel_pch.c > b/drivers/gpu/drm/i915/intel_pch.c index 15f8bff141f9..1035d3d46fd8 > 100644 --- a/drivers/gpu/drm/i915/intel_pch.c > +++ b/drivers/gpu/drm/i915/intel_pch.c > @@ -79,7 +79,6 @@ intel_pch_type(const struct drm_i915_private > *dev_priv, unsigned short id) WARN_ON(!IS_ICELAKE(dev_priv)); > return PCH_ICP; > case INTEL_PCH_MCC_DEVICE_ID_TYPE: > - case INTEL_PCH_MCC2_DEVICE_ID_TYPE: > DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n"); > WARN_ON(!IS_ELKHARTLAKE(dev_priv)); > return PCH_MCC; > @@ -87,6 +86,11 @@ intel_pch_type(const struct drm_i915_private > *dev_priv, unsigned short id) DRM_DEBUG_KMS("Found Tiger Lake LP > PCH\n"); WARN_ON(!IS_TIGERLAKE(dev_priv)); > return PCH_TGP; > + case INTEL_PCH_JSP_DEVICE_ID_TYPE: > + case INTEL_PCH_JSP2_DEVICE_ID_TYPE: > + DRM_DEBUG_KMS("Found Jasper Lake PCH\n"); > + WARN_ON(!IS_ELKHARTLAKE(dev_priv)); > + return PCH_JSP; > default: > return PCH_NONE; > } > diff --git a/drivers/gpu/drm/i915/intel_pch.h > b/drivers/gpu/drm/i915/intel_pch.h index c29c81ec7971..f4dc18c34291 > 100644 --- a/drivers/gpu/drm/i915/intel_pch.h > +++ b/drivers/gpu/drm/i915/intel_pch.h > @@ -23,6 +23,7 @@ enum intel_pch { > PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */ > PCH_CNP, /* Cannon/Comet Lake PCH */ > PCH_ICP, /* Ice Lake PCH */ > + PCH_JSP, /* Jasper Lake PCH */ > PCH_MCC, /* Mule Creek Canyon PCH */ > PCH_TGP, /* Tiger Lake PCH */ > }; > @@ -44,14 +45,16 @@ enum intel_pch { > #define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680 > #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480 > #define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00 > -#define INTEL_PCH_MCC2_DEVICE_ID_TYPE 0x3880 > #define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080 > +#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80 > +#define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880 > #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 > #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 > #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu > q35 has 2918 */ > #define INTEL_PCH_TYPE(dev_priv) > ((dev_priv)->pch_type) #define INTEL_PCH_ID(dev_priv) > ((dev_priv)->pch_id) +#define HAS_PCH_JSP(dev_priv) > (INTEL_PCH_TYPE(dev_priv) == PCH_JSP) #define > HAS_PCH_MCC(dev_priv) > (INTEL_PCH_TYPE(dev_priv) == PCH_MCC) #define > HAS_PCH_TGP(dev_priv) > (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) #define > HAS_PCH_ICP(dev_priv) > (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index d20ca02d3166..81e9ed48ce9f 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2248,11 +2248,18 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP; tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect; pins = hpd_tgp; + } else if (HAS_PCH_JSP(dev_priv)) { + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; + tc_hotplug_trigger = 0; + pins = hpd_tgp; } else if (HAS_PCH_MCC(dev_priv)) { ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1); pins = hpd_icp; } else { + WARN(!HAS_PCH_ICP(dev_priv), + "Unrecognized PCH type 0x%x\n", INTEL_PCH_TYPE(dev_priv)); + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect; @@ -3373,15 +3380,27 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, } /* - * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the + * EHL/JSL don't need most of gen11_hpd_irq_setup, they're handling only the * equivalent of SDE. + * + * Note that MCC and JSP have different port C pin mappings, hence the use of + * ICP's masks & tables (hpd C on TC1) vs TGP's masks & tables (hpd C on DDIC) + * depending on platform. */ static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) { - icp_hpd_irq_setup(dev_priv, - SDE_DDI_MASK_ICP, SDE_TC_HOTPLUG_ICP(PORT_TC1), - ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1), - hpd_icp); + if (HAS_PCH_JSP(dev_priv)) + icp_hpd_irq_setup(dev_priv, + SDE_DDI_MASK_TGP, 0, + TGP_DDI_HPD_ENABLE_MASK, 0, + hpd_tgp); + else + icp_hpd_irq_setup(dev_priv, + SDE_DDI_MASK_ICP, + SDE_TC_HOTPLUG_ICP(PORT_TC1), + ICP_DDI_HPD_ENABLE_MASK, + ICP_TC_HPD_ENABLE(PORT_TC1), + hpd_icp); } static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) @@ -4315,7 +4334,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) if (I915_HAS_HOTPLUG(dev_priv)) dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; } else { - if (HAS_PCH_MCC(dev_priv)) + if (HAS_PCH_MCC(dev_priv) || HAS_PCH_JSP(dev_priv)) dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup; else if (INTEL_GEN(dev_priv) >= 11) dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup; diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c index 15f8bff141f9..1035d3d46fd8 100644 --- a/drivers/gpu/drm/i915/intel_pch.c +++ b/drivers/gpu/drm/i915/intel_pch.c @@ -79,7 +79,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) WARN_ON(!IS_ICELAKE(dev_priv)); return PCH_ICP; case INTEL_PCH_MCC_DEVICE_ID_TYPE: - case INTEL_PCH_MCC2_DEVICE_ID_TYPE: DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n"); WARN_ON(!IS_ELKHARTLAKE(dev_priv)); return PCH_MCC; @@ -87,6 +86,11 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n"); WARN_ON(!IS_TIGERLAKE(dev_priv)); return PCH_TGP; + case INTEL_PCH_JSP_DEVICE_ID_TYPE: + case INTEL_PCH_JSP2_DEVICE_ID_TYPE: + DRM_DEBUG_KMS("Found Jasper Lake PCH\n"); + WARN_ON(!IS_ELKHARTLAKE(dev_priv)); + return PCH_JSP; default: return PCH_NONE; } diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h index c29c81ec7971..f4dc18c34291 100644 --- a/drivers/gpu/drm/i915/intel_pch.h +++ b/drivers/gpu/drm/i915/intel_pch.h @@ -23,6 +23,7 @@ enum intel_pch { PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */ PCH_CNP, /* Cannon/Comet Lake PCH */ PCH_ICP, /* Ice Lake PCH */ + PCH_JSP, /* Jasper Lake PCH */ PCH_MCC, /* Mule Creek Canyon PCH */ PCH_TGP, /* Tiger Lake PCH */ }; @@ -44,14 +45,16 @@ enum intel_pch { #define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480 #define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00 -#define INTEL_PCH_MCC2_DEVICE_ID_TYPE 0x3880 #define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080 +#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80 +#define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) +#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP) #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC) #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
The Jasper Lake PCH follows ICP/TGP's south display behavior and is identical to MCC graphics-wise except that it does not use the unusual (port C -> TC1) pin mapping that MCC does. Also, it turns out the extra PCH ID that we had previously thought was a form of MCC is actually a second ID for JSP (i.e., port C uses the port C pins instead of the TC1 pins). v2: - Also update the port masks (not just the pin table) in mcc_hpd_irq_setup. (Vivek) Cc: José Roberto de Souza <jose.souza@intel.com> Cc: James Ausmus <james.ausmus@intel.com> Cc: Vivek Kasireddy <vivek.kasireddy@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 31 +++++++++++++++++++++++++------ drivers/gpu/drm/i915/intel_pch.c | 6 +++++- drivers/gpu/drm/i915/intel_pch.h | 5 ++++- 3 files changed, 34 insertions(+), 8 deletions(-)