diff mbox series

[03/11] drm/i915/tgl: Add HDC Pipeline Flush

Message ID 20191015154449.10338-3-mika.kuoppala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series [01/11] drm/i915/tgl: Add IS_TGL_REVID | expand

Commit Message

Mika Kuoppala Oct. 15, 2019, 3:44 p.m. UTC
Add hdc pipeline flush to ensure memory state is coherent
in L3 when we are done.

v2: Flush also in breadcrumbs (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c          | 5 ++++-
 2 files changed, 5 insertions(+), 1 deletion(-)

Comments

Chris Wilson Oct. 15, 2019, 3:55 p.m. UTC | #1
Quoting Mika Kuoppala (2019-10-15 16:44:41)
> Add hdc pipeline flush to ensure memory state is coherent
> in L3 when we are done.
> 
> v2: Flush also in breadcrumbs (Chris)
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> @@ -3416,7 +3417,9 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
>                                       PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
>                                       PIPE_CONTROL_DEPTH_CACHE_FLUSH |
>                                       PIPE_CONTROL_DC_FLUSH_ENABLE |
> -                                     PIPE_CONTROL_FLUSH_ENABLE);
> +                                     PIPE_CONTROL_FLUSH_ENABLE |
> +                                     PIPE_CONTROL_HDC_PIPELINE_FLUSH);
> +

Bonus!
-Chris
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 4586a6a1fad4..d6bf272d8c59 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -235,6 +235,7 @@ 
 #define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
 #define   PIPE_CONTROL_L3_RO_CACHE_INVALIDATE		(1<<10) /* gen12 */
 #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
+#define   PIPE_CONTROL_HDC_PIPELINE_FLUSH		(1<<9)  /* gen 12 */
 #define   PIPE_CONTROL_NOTIFY				(1<<8)
 #define   PIPE_CONTROL_FLUSH_ENABLE			(1<<7) /* gen7+ */
 #define   PIPE_CONTROL_DC_FLUSH_ENABLE			(1<<5)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 2fe339228b82..27b5259f2f66 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3206,6 +3206,7 @@  static int gen12_emit_flush_render(struct i915_request *request,
 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 		flags |= PIPE_CONTROL_FLUSH_ENABLE;
+		flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
 
 		flags |= PIPE_CONTROL_STORE_DATA_INDEX;
 		flags |= PIPE_CONTROL_QW_WRITE;
@@ -3416,7 +3417,9 @@  gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
 				      PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
 				      PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 				      PIPE_CONTROL_DC_FLUSH_ENABLE |
-				      PIPE_CONTROL_FLUSH_ENABLE);
+				      PIPE_CONTROL_FLUSH_ENABLE |
+				      PIPE_CONTROL_HDC_PIPELINE_FLUSH);
+
 
 	return gen12_emit_fini_breadcrumb_footer(request, cs);
 }