From patchwork Wed Oct 23 15:29:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janusz Krzysztofik X-Patchwork-Id: 11207045 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A5951515 for ; Wed, 23 Oct 2019 15:29:42 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E672920650 for ; Wed, 23 Oct 2019 15:29:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E672920650 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7DE446EB0E; Wed, 23 Oct 2019 15:29:41 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8308E6EB0E; Wed, 23 Oct 2019 15:29:37 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Oct 2019 08:29:37 -0700 X-IronPort-AV: E=Sophos;i="5.68,221,1569308400"; d="scan'208";a="202027951" Received: from jkrzyszt-desk.igk.intel.com ([172.22.244.17]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Oct 2019 08:29:34 -0700 From: Janusz Krzysztofik To: igt-dev@lists.freedesktop.org Date: Wed, 23 Oct 2019 17:29:17 +0200 Message-Id: <20191023152917.647-3-janusz.krzysztofik@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191023152917.647-1-janusz.krzysztofik@linux.intel.com> References: <20191023152917.647-1-janusz.krzysztofik@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC PATCH v2 3/3] tests/gem_exec_reloc: Detect minimum batch size X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The basic-range subtest have been already taught to calculate softpin offsets from minimum batch size, however it still uses a hardcoded value of 4kB. On future backends with possibly bigger minimum batch sizes this subtest will fail as buffer objects may overlap. Detect minimum batch size instead of using a hardcoded value. To avoid conflicts with addresses occupied by other users, do that only when running on full PPGTT. Platforms without full PPGTT are not expected to support backends with minimum batch sizes greater than 4kB. Signed-off-by: Janusz Krzysztofik --- tests/i915/gem_exec_reloc.c | 41 +++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c index 61401ea7..b71fe0be 100644 --- a/tests/i915/gem_exec_reloc.c +++ b/tests/i915/gem_exec_reloc.c @@ -511,6 +511,42 @@ static uint64_t gen8_canonical_address(uint64_t address) return sign_extend(address, 47); } +static int local_gem_minimum_batch_order(int fd) +{ + struct drm_i915_gem_exec_object2 obj; + struct drm_i915_gem_execbuffer2 execbuf; + uint64_t gtt_size = gem_aperture_size(fd); + const uint32_t bbe = MI_BATCH_BUFFER_END; + int batch_order = 12; + uint64_t batch_size = 1ull << batch_order; /* 4096 */ + + if (!gem_uses_full_ppgtt(fd) || !gem_has_softpin(fd)) + return batch_order; + + memset(&obj, 0, sizeof(obj)); + memset(&execbuf, 0, sizeof(execbuf)); + + obj.handle = gem_create(fd, 4096); + obj.flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + while (batch_size < gtt_size) { + obj.offset = gtt_size - batch_size; + obj.offset = gen8_canonical_address(obj.offset); + gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe)); + execbuf.buffers_ptr = to_user_pointer(&obj); + execbuf.buffer_count = 1; + if (!__gem_execbuf(fd, &execbuf)) { + igt_debug("batch_order=%d, batch_size=%llx\n", + batch_order, (long long)batch_size); + break; + } + batch_size <<= 1; + batch_order++; + } + gem_close(fd, obj.handle); + igt_require(batch_size < gtt_size); + return batch_order; +} + static void basic_range(int fd, unsigned flags) { struct drm_i915_gem_relocation_entry reloc[128]; @@ -520,8 +556,8 @@ static void basic_range(int fd, unsigned flags) uint64_t gtt_size = gem_aperture_size(fd); const uint32_t bbe = MI_BATCH_BUFFER_END; igt_spin_t *spin = NULL; - int batch_order = 12; - uint64_t batch_size = 1ull << batch_order; /* 4096 */ + int batch_order = local_gem_minimum_batch_order(fd); + uint64_t batch_size = 1ull << batch_order; int count, n; igt_require(gem_has_softpin(fd)); @@ -530,6 +566,7 @@ static void basic_range(int fd, unsigned flags) ; count -= batch_order; + igt_require(count); memset(obj, 0, sizeof(obj)); memset(reloc, 0, sizeof(reloc));