From patchwork Fri Oct 25 12:55:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gwan-gyeong Mun X-Patchwork-Id: 11212295 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4A0F414E5 for ; Fri, 25 Oct 2019 12:55:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3244821929 for ; Fri, 25 Oct 2019 12:55:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3244821929 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C850C89FD1; Fri, 25 Oct 2019 12:55:47 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id B66BF89F41 for ; Fri, 25 Oct 2019 12:55:43 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Oct 2019 05:55:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,228,1569308400"; d="scan'208";a="201801021" Received: from helsinki.fi.intel.com ([10.237.66.157]) by orsmga003.jf.intel.com with ESMTP; 25 Oct 2019 05:55:41 -0700 From: Gwan-gyeong Mun To: intel-gfx@lists.freedesktop.org Date: Fri, 25 Oct 2019 15:55:26 +0300 Message-Id: <20191025125530.1015447-2-gwan-gyeong.mun@intel.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191025125530.1015447-1-gwan-gyeong.mun@intel.com> References: <20191025125530.1015447-1-gwan-gyeong.mun@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 1/5] drm/i915: Add whether or not to enable an each of Video DIP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Because DP ports don't use set_infoframes() / intel_write_infoframe() machanisms, DP ports requires a handling of enabling/disabling of each Video DIP when a changing usage of video DIP for SDP transmission such as whether or not to use HDR. For now it only adds enable_infoframe() callback for hsw platform. v2: Minor style fix Signed-off-by: Gwan-gyeong Mun --- .../drm/i915/display/intel_display_types.h | 4 +++ drivers/gpu/drm/i915/display/intel_hdmi.c | 36 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_hdmi.h | 3 ++ 3 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index bac40482a2aa..a541c8cc8d83 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1305,6 +1305,10 @@ struct intel_digital_port { const struct intel_crtc_state *crtc_state, unsigned int type, void *frame, ssize_t len); + void (*enable_infoframe)(struct intel_encoder *encoder, + bool enable, + const struct intel_crtc_state *crtc_state, + unsigned int type); void (*set_infoframes)(struct intel_encoder *encoder, bool enable, const struct intel_crtc_state *crtc_state, diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index b54ccbb5aad5..b62afeccd44e 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -559,6 +559,24 @@ static void hsw_read_infoframe(struct intel_encoder *encoder, type, i >> 2)); } +static void hsw_enable_infoframe(struct intel_encoder *encoder, + bool enable, + const struct intel_crtc_state *crtc_state, + unsigned int type) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); + u32 val = I915_READ(ctl_reg); + + if (enable) + val |= hsw_infoframe_enable(type); + else + val &= ~hsw_infoframe_enable(type); + + I915_WRITE(ctl_reg, val); + POSTING_READ(ctl_reg); +} + static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { @@ -586,6 +604,23 @@ static const u8 infoframe_type_to_idx[] = { HDMI_INFOFRAME_TYPE_DRM, }; +void intel_enable_infoframe(struct intel_encoder *encoder, + bool enable, + const struct intel_crtc_state *crtc_state, + unsigned int type) +{ + struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); + + if (dig_port->enable_infoframe) { + dig_port->enable_infoframe(encoder, enable, crtc_state, type); + } else { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + + DRM_DEBUG_KMS("GEN%d enable_infoframe() callback is not implemented!", + INTEL_GEN(dev_priv)); + } +} + u32 intel_hdmi_infoframe_enable(unsigned int type) { int i; @@ -3104,6 +3139,7 @@ void intel_infoframe_init(struct intel_digital_port *intel_dig_port) } else { intel_dig_port->write_infoframe = hsw_write_infoframe; intel_dig_port->read_infoframe = hsw_read_infoframe; + intel_dig_port->enable_infoframe = hsw_enable_infoframe; intel_dig_port->set_infoframes = hsw_set_infoframes; intel_dig_port->infoframes_enabled = hsw_infoframes_enabled; } diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h index cf1ea5427639..86f925526514 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.h +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h @@ -48,5 +48,8 @@ void intel_read_infoframe(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, enum hdmi_infoframe_type type, union hdmi_infoframe *frame); +void intel_enable_infoframe(struct intel_encoder *encoder, bool enable, + const struct intel_crtc_state *crtc_state, + unsigned int type); #endif /* __INTEL_HDMI_H__ */