| Message ID | 20191029095856.25431-5-matthew.auld@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/7] drm/i915: define i915_ggtt_has_aperture | expand |
Quoting Matthew Auld (2019-10-29 09:58:54) > From: Michal Wajdeczko <michal.wajdeczko@intel.com> > > HWS placement restrictions can't just rely on HAS_LLC flag. > > Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> > Signed-off-by: Matthew Auld <matthew.auld@intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 9cc1ea6519ec..355523114c71 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -528,7 +528,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine, > unsigned int flags; > > flags = PIN_GLOBAL; > - if (!HAS_LLC(engine->i915)) > + if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) > /* > * On g33, we cannot place HWS above 256MiB, so > * restrict its pinning to the low mappable arena. How we will laugh if it turns out future HW cannot handle having the HWSP placed anywhere! :) Acked-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 9cc1ea6519ec..355523114c71 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -528,7 +528,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine, unsigned int flags; flags = PIN_GLOBAL; - if (!HAS_LLC(engine->i915)) + if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) /* * On g33, we cannot place HWS above 256MiB, so * restrict its pinning to the low mappable arena.