| Message ID | 20191101142024.13877-1-jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] drm/i915: update rawclk also on resume | expand |
On Fri, Nov 01, 2019 at 04:20:24PM +0200, Jani Nikula wrote: > Since CNP it's possible for rawclk to have two different values, 19.2 > and 24 MHz. If the value indicated by SFUSE_STRAP register is different > from the power on default for PCH_RAWCLK_FREQ, we'll end up having a > mismatch between the rawclk hardware and software states after > suspend/resume. On previous platforms this used to work by accident, > because the power on defaults worked just fine. > > Update the rawclk also on resume. The natural place to do this would be > intel_modeset_init_hw(), however VLV/CHV need it done before > intel_power_domains_init_hw(). Thus put it there even if it feels > slightly out of place. > > v2: Call intel_update_rawclck() in intel_power_domains_init_hw() for all > platforms (Ville). > > Reported-by: Shawn Lee <shawn.c.lee@intel.com> > Cc: Shawn Lee <shawn.c.lee@intel.com> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++ > drivers/gpu/drm/i915/i915_drv.c | 3 --- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 707ac110e271..ce1b64f4dd44 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -5015,6 +5015,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) > > power_domains->initializing = true; > > + /* Must happen before power domain init on VLV/CHV */ > + intel_update_rawclk(i915); > + > if (INTEL_GEN(i915) >= 11) { > icl_display_core_init(i915, resume); > } else if (IS_CANNONLAKE(i915)) { > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 3340485c12e3..71944399dcfc 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct drm_i915_private *i915) > if (ret) > goto cleanup_vga_client; > > - /* must happen before intel_power_domains_init_hw() on VLV/CHV */ > - intel_update_rawclk(i915); > - > intel_power_domains_init_hw(i915, false); > > intel_csr_ucode_init(i915); > -- > 2.20.1
On Mon, 04 Nov 2019, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Fri, Nov 01, 2019 at 04:20:24PM +0200, Jani Nikula wrote: >> Since CNP it's possible for rawclk to have two different values, 19.2 >> and 24 MHz. If the value indicated by SFUSE_STRAP register is different >> from the power on default for PCH_RAWCLK_FREQ, we'll end up having a >> mismatch between the rawclk hardware and software states after >> suspend/resume. On previous platforms this used to work by accident, >> because the power on defaults worked just fine. >> >> Update the rawclk also on resume. The natural place to do this would be >> intel_modeset_init_hw(), however VLV/CHV need it done before >> intel_power_domains_init_hw(). Thus put it there even if it feels >> slightly out of place. >> >> v2: Call intel_update_rawclck() in intel_power_domains_init_hw() for all >> platforms (Ville). >> >> Reported-by: Shawn Lee <shawn.c.lee@intel.com> >> Cc: Shawn Lee <shawn.c.lee@intel.com> >> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Thanks for the testing and review, pushed to dinq. BR, Jani. > >> --- >> drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++ >> drivers/gpu/drm/i915/i915_drv.c | 3 --- >> 2 files changed, 3 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c >> index 707ac110e271..ce1b64f4dd44 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display_power.c >> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c >> @@ -5015,6 +5015,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) >> >> power_domains->initializing = true; >> >> + /* Must happen before power domain init on VLV/CHV */ >> + intel_update_rawclk(i915); >> + >> if (INTEL_GEN(i915) >= 11) { >> icl_display_core_init(i915, resume); >> } else if (IS_CANNONLAKE(i915)) { >> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c >> index 3340485c12e3..71944399dcfc 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.c >> +++ b/drivers/gpu/drm/i915/i915_drv.c >> @@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct drm_i915_private *i915) >> if (ret) >> goto cleanup_vga_client; >> >> - /* must happen before intel_power_domains_init_hw() on VLV/CHV */ >> - intel_update_rawclk(i915); >> - >> intel_power_domains_init_hw(i915, false); >> >> intel_csr_ucode_init(i915); >> -- >> 2.20.1
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 707ac110e271..ce1b64f4dd44 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5015,6 +5015,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) power_domains->initializing = true; + /* Must happen before power domain init on VLV/CHV */ + intel_update_rawclk(i915); + if (INTEL_GEN(i915) >= 11) { icl_display_core_init(i915, resume); } else if (IS_CANNONLAKE(i915)) { diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 3340485c12e3..71944399dcfc 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct drm_i915_private *i915) if (ret) goto cleanup_vga_client; - /* must happen before intel_power_domains_init_hw() on VLV/CHV */ - intel_update_rawclk(i915); - intel_power_domains_init_hw(i915, false); intel_csr_ucode_init(i915);
Since CNP it's possible for rawclk to have two different values, 19.2 and 24 MHz. If the value indicated by SFUSE_STRAP register is different from the power on default for PCH_RAWCLK_FREQ, we'll end up having a mismatch between the rawclk hardware and software states after suspend/resume. On previous platforms this used to work by accident, because the power on defaults worked just fine. Update the rawclk also on resume. The natural place to do this would be intel_modeset_init_hw(), however VLV/CHV need it done before intel_power_domains_init_hw(). Thus put it there even if it feels slightly out of place. v2: Call intel_update_rawclck() in intel_power_domains_init_hw() for all platforms (Ville). Reported-by: Shawn Lee <shawn.c.lee@intel.com> Cc: Shawn Lee <shawn.c.lee@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++ drivers/gpu/drm/i915/i915_drv.c | 3 --- 2 files changed, 3 insertions(+), 3 deletions(-)