diff mbox series

[i-g-t,4/7] tests/i915: Skip if secure batches is not available

Message ID 20191113154913.8787-4-mika.kuoppala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series [i-g-t,1/7] lib/igt_dummyload: Send batch as first | expand

Commit Message

Mika Kuoppala Nov. 13, 2019, 3:49 p.m. UTC 
From: "Kuoppala, Mika" <mika.kuoppala@intel.com>

If we can't do secure execbuf, there is no point in trying.

Signed-off-by: Kuoppala, Mika <mika.kuoppala@intel.com>
---
 tests/i915/gem_exec_params.c   | 16 ++++++++++++++++
 tests/i915/gem_mocs_settings.c | 14 ++++++++++++++
 tests/perf_pmu.c               | 11 +++++++++++
 3 files changed, 41 insertions(+)
diff mbox series

Patch

diff --git a/tests/i915/gem_exec_params.c b/tests/i915/gem_exec_params.c
index 8f15e645..c5517b07 100644
--- a/tests/i915/gem_exec_params.c
+++ b/tests/i915/gem_exec_params.c
@@ -193,6 +193,19 @@  static void test_batch_first(int fd)
 	gem_close(fd, obj[0].handle);
 }
 
+static int has_secure_batches(const int fd)
+{
+	int v = -1;
+	drm_i915_getparam_t gp;
+
+	gp.param = I915_PARAM_HAS_SECURE_BATCHES;
+	gp.value = &v;
+
+	igt_assert_eq(drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp), 0);
+
+	return v;
+}
+
 struct drm_i915_gem_execbuffer2 execbuf;
 struct drm_i915_gem_exec_object2 gem_exec[1];
 uint32_t batch[2] = {MI_BATCH_BUFFER_END};
@@ -340,6 +353,8 @@  igt_main
 	}
 
 	igt_subtest("secure-non-root") {
+		igt_require(has_secure_batches(fd));
+
 		igt_fork(child, 1) {
 			igt_drop_root();
 
@@ -352,6 +367,7 @@  igt_main
 
 	igt_subtest("secure-non-master") {
 		igt_require(__igt_device_set_master(fd) == 0); /* Requires root privilege */
+		igt_require(has_secure_batches(fd));
 
 		igt_device_drop_master(fd);
 		execbuf.flags = I915_EXEC_RENDER | I915_EXEC_SECURE;
diff --git a/tests/i915/gem_mocs_settings.c b/tests/i915/gem_mocs_settings.c
index fc2ccb21..82eb8a3f 100644
--- a/tests/i915/gem_mocs_settings.c
+++ b/tests/i915/gem_mocs_settings.c
@@ -225,6 +225,19 @@  static uint32_t get_engine_base(int fd, uint32_t engine)
 	}
 }
 
+static int has_secure_batches(const int fd)
+{
+	int v = -1;
+	drm_i915_getparam_t gp;
+
+	gp.param = I915_PARAM_HAS_SECURE_BATCHES;
+	gp.value = &v;
+
+	igt_assert_eq(drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp), 0);
+
+	return v;
+}
+
 #define MI_STORE_REGISTER_MEM_64_BIT_ADDR	((0x24 << 23) | 2)
 
 static int create_read_batch(struct drm_i915_gem_relocation_entry *reloc,
@@ -566,6 +579,7 @@  igt_main
 		igt_require_gem(fd);
 		gem_require_mocs_registers(fd);
 		igt_require(get_mocs_settings(fd, &table, false));
+		igt_require(has_secure_batches(fd));
 	}
 
 	for (e = intel_execution_engines; e->name; e++) {
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index e2bd2cc5..296d04c6 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -893,6 +893,16 @@  static int wait_vblank(int fd, union drm_wait_vblank *vbl)
 	return err;
 }
 
+static int has_secure_batches(const int fd)
+{
+	int v = -1;
+	drm_i915_getparam_t gp;
+	gp.param = I915_PARAM_HAS_SECURE_BATCHES;
+	gp.value = &v;
+	igt_assert_eq(drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp), 0);
+	return v;
+}
+
 static void
 event_wait(int gem_fd, const struct intel_execution_engine2 *e)
 {
@@ -910,6 +920,7 @@  event_wait(int gem_fd, const struct intel_execution_engine2 *e)
 
 	devid = intel_get_drm_devid(gem_fd);
 	igt_require(intel_gen(devid) >= 7);
+	igt_require(has_secure_batches(fd));
 	igt_skip_on(IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid));
 
 	kmstest_set_vt_graphics_mode();