| Message ID | 20191114160522.9699-6-maarten.lankhorst@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/11] HAX to make DSC work on the icelake test system | expand |
On Thu, Nov 14, 2019 at 05:05:17PM +0100, Maarten Lankhorst wrote: > Make vdsc work when no output is enabled. The big joiner needs VDSC > on the slave, so enable it and set the appropriate bits. > Also update timestamping constants, because slave crtc's are not > updated in drm_atomic_helper_update_legacy_modeset_state(). > > This should be enough to bring up CRTC's in a big joiner configuration, > without any plane configuration on the second pipe yet. > > HOWEVER, we still bring up the crtc's in the wrong order. We need to > make sure that the master crtc is brought up after the slave crtc. > This is done correctly later in this series. > > The next steps are to enable planes correctly, and make sure we enable > and update both master and slave in the correct order. > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 48 ++- > drivers/gpu/drm/i915/display/intel_display.c | 399 ++++++++++++------ > .../drm/i915/display/intel_display_types.h | 22 + > drivers/gpu/drm/i915/display/intel_dp.c | 21 +- > drivers/gpu/drm/i915/display/intel_vdsc.c | 122 ++++-- > drivers/gpu/drm/i915/display/intel_vdsc.h | 2 + > 6 files changed, 408 insertions(+), 206 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 8f817de34460..1215f619da36 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -2218,13 +2218,6 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, > intel_phy_is_tc(dev_priv, phy)) > intel_display_power_get(dev_priv, > intel_ddi_main_link_aux_domain(dig_port)); > - > - /* > - * VDSC power is needed when DSC is enabled > - */ > - if (crtc_state->dsc.compression_enable) > - intel_display_power_get(dev_priv, > - intel_dsc_power_domain(crtc_state)); > } > > void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) > @@ -3557,7 +3550,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, > > /* 7.l Configure and enable FEC if needed */ > intel_ddi_enable_fec(encoder, crtc_state); > - intel_dsc_enable(encoder, crtc_state); > + if (!crtc_state->bigjoiner) > + intel_dsc_enable(encoder, crtc_state); > } > > static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, > @@ -3629,7 +3623,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, > if (!is_mst) > intel_ddi_enable_pipe_clock(crtc_state); > > - intel_dsc_enable(encoder, crtc_state); > + if (!crtc_state->bigjoiner) > + intel_dsc_enable(encoder, crtc_state); > } > > static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, > @@ -4252,19 +4247,18 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, > crtc_state->min_voltage_level = 2; > } > > -void intel_ddi_get_config(struct intel_encoder *encoder, > - struct intel_crtc_state *pipe_config) > +static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, > + struct intel_crtc_state *pipe_config) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); > enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; > u32 temp, flags = 0; > > - /* XXX: DSI transcoder paranoia */ > - if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) > + temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); > + if (!(temp & TRANS_DDI_FUNC_ENABLE)) > return; > > - temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); > if (temp & TRANS_DDI_PHSYNC) > flags |= DRM_MODE_FLAG_PHSYNC; > else > @@ -4350,6 +4344,29 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > default: > break; > } > +} > + > +void intel_ddi_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *pipe_config) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; > + > + /* XXX: DSI transcoder paranoia */ > + if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) > + return; > + > + intel_ddi_read_func_ctl(encoder, pipe_config); > + if (pipe_config->bigjoiner_slave) { > + /* read out pipe settings from master */ > + enum transcoder save = pipe_config->cpu_transcoder; > + > + /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */ > + WARN_ON(pipe_config->output_types); > + pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe; That's pretty horrible. I don't understand the enable/disable sequence enough to know what we need to configure/enable where exactly. Bspec just says: "2. Follow the steps to Enable Planes, Pipe, and Transcoder for pipe C, but do not configure or enable transcoder C. 3. Follow the steps to Enable Planes, Pipe, and Transcoder for pipe B and transcoder B." So we need to enable transcoder for pipe C but not enable transcoder C? I have no idea what actually means. > + intel_ddi_read_func_ctl(encoder, pipe_config); > + pipe_config->cpu_transcoder = save; > + } > > if (encoder->type == INTEL_OUTPUT_EDP) > tgl_dc3co_exitline_get_config(pipe_config); > @@ -4377,7 +4394,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; > } > > - intel_ddi_clock_get(encoder, pipe_config); > + if (!pipe_config->bigjoiner_slave) > + intel_ddi_clock_get(encoder, pipe_config); > > if (IS_GEN9_LP(dev_priv)) > pipe_config->lane_lat_optim_mask = > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 2dc63ef5caf8..94e4cab00a66 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -6583,6 +6583,45 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc) > I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val); > } > > +static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, > + struct intel_crtc_state *crtc_state) > +{ > + struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc); > + struct intel_crtc_state *master_crtc_state; > + struct drm_connector_state *conn_state; > + struct drm_connector *conn; > + struct intel_encoder *encoder = NULL; > + int i; > + > + if (crtc_state->bigjoiner_slave) > + master = crtc_state->bigjoiner_linked_crtc; > + > + master_crtc_state = intel_atomic_get_new_crtc_state(state, master); > + > + for_each_new_connector_in_state(&state->base, conn, conn_state, i) { > + if (conn_state->crtc != &master->base) > + continue; > + > + encoder = to_intel_encoder(conn_state->best_encoder); > + break; > + } > + > + if (!crtc_state->bigjoiner_slave) { > + /* need to enable VDSC, which we skipped in pre-enable */ > + intel_dsc_enable(encoder, crtc_state); > + } else { > + /* > + * Enable sequence steps 1-7 on bigjoiner master > + */ > + intel_encoders_pre_pll_enable(master, master_crtc_state, state); > + intel_enable_shared_dpll(master_crtc_state); > + intel_encoders_pre_enable(master, master_crtc_state, state); > + > + /* and DSC on slave */ > + intel_dsc_enable(NULL, crtc_state); > + } > +} > + > static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > struct intel_atomic_state *state) > { > @@ -6596,40 +6635,41 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > if (WARN_ON(intel_crtc->active)) > return; > > - intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state); > + if (!pipe_config->bigjoiner) { > + intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state); > > - if (pipe_config->shared_dpll) > - intel_enable_shared_dpll(pipe_config); > + if (pipe_config->shared_dpll) > + intel_enable_shared_dpll(pipe_config); > > - intel_encoders_pre_enable(intel_crtc, pipe_config, state); > + intel_encoders_pre_enable(intel_crtc, pipe_config, state); > + } else { > + icl_ddi_bigjoiner_pre_enable(state, pipe_config); > + } > > - if (intel_crtc_has_dp_encoder(pipe_config)) > - intel_dp_set_m_n(pipe_config, M1_N1); > + intel_set_pipe_src_size(pipe_config); > + if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) > + bdw_set_pipemisc(pipe_config); > > - if (!transcoder_is_dsi(cpu_transcoder)) > - intel_set_transcoder_timings(pipe_config); > + if (!pipe_config->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) { > + if (intel_crtc_has_dp_encoder(pipe_config)) > + intel_dp_set_m_n(pipe_config, M1_N1); > > - if (INTEL_GEN(dev_priv) >= 11) > - icl_enable_trans_port_sync(pipe_config); > + if (INTEL_GEN(dev_priv) >= 11) > + icl_enable_trans_port_sync(pipe_config); > > - intel_set_pipe_src_size(pipe_config); > + intel_set_transcoder_timings(pipe_config); > > - if (cpu_transcoder != TRANSCODER_EDP && > - !transcoder_is_dsi(cpu_transcoder)) { > - I915_WRITE(PIPE_MULT(cpu_transcoder), > - pipe_config->pixel_multiplier - 1); > - } > + if (cpu_transcoder != TRANSCODER_EDP) > + I915_WRITE(PIPE_MULT(cpu_transcoder), > + pipe_config->pixel_multiplier - 1); > > - if (pipe_config->has_pch_encoder) { > - intel_cpu_transcoder_set_m_n(pipe_config, > - &pipe_config->fdi_m_n, NULL); > - } > + if (pipe_config->has_pch_encoder) { > + intel_cpu_transcoder_set_m_n(pipe_config, > + &pipe_config->fdi_m_n, NULL); > + } > > - if (!transcoder_is_dsi(cpu_transcoder)) > haswell_set_pipeconf(pipe_config); > - > - if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) > - bdw_set_pipemisc(pipe_config); > + } > > intel_crtc->active = true; > > @@ -6657,7 +6697,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > if (INTEL_GEN(dev_priv) >= 11) > icl_set_pipe_chicken(intel_crtc); > > - if (!transcoder_is_dsi(cpu_transcoder)) > + if (!pipe_config->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) > intel_ddi_enable_transcoder_func(pipe_config); > > if (dev_priv->display.initial_watermarks != NULL) > @@ -6667,8 +6707,10 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > icl_pipe_mbus_enable(intel_crtc); > > /* XXX: Do the pipe assertions at the right place for BXT DSI. */ > - if (!transcoder_is_dsi(cpu_transcoder)) > + if (!pipe_config->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) > intel_enable_pipe(pipe_config); > + else > + trace_intel_pipe_enable(intel_crtc); > > if (pipe_config->has_pch_encoder) > lpt_pch_enable(state, pipe_config); > @@ -6796,9 +6838,27 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, > else > ironlake_pfit_disable(old_crtc_state); > > - intel_encoders_post_disable(intel_crtc, old_crtc_state, state); > + if (old_crtc_state->bigjoiner) { > + struct intel_crtc *master; > + struct intel_crtc_state *master_crtc_state; > > - intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state); > + /* ports are disabled from the slave, after it deconfigures */ > + if (!old_crtc_state->bigjoiner_slave) > + return; > + > + master = old_crtc_state->bigjoiner_linked_crtc; > + master_crtc_state = intel_atomic_get_old_crtc_state(state, master); > + > + intel_ddi_disable_pipe_clock(old_crtc_state); > + > + /* disable ports on the master crtc */ > + intel_encoders_post_disable(master, master_crtc_state, state); > + intel_encoders_post_pll_disable(master, master_crtc_state, state); > + } else { > + intel_encoders_post_disable(intel_crtc, old_crtc_state, state); > + > + intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state); > + } > } > > static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) > @@ -6968,6 +7028,9 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) > if (crtc_state->shared_dpll) > mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); > > + if (crtc_state->dsc.compression_enable) > + mask |= BIT_ULL(intel_dsc_power_domain(crtc_state)); > + > return mask; > } > > @@ -7559,6 +7622,30 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) > return pixel_rate; > } > > +static void intel_encoder_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state) > +{ > + struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; > + > + encoder->get_config(encoder, crtc_state); > + > + *pipe_mode = crtc_state->hw.adjusted_mode; > + if (crtc_state->bigjoiner) { > + /* > + * transcoder is programmed to the full mode, > + * but pipje timings are half of the transcoder mode > + */ > + pipe_mode->crtc_hdisplay /= 2; > + pipe_mode->crtc_hblank_start /= 2; > + pipe_mode->crtc_hblank_end /= 2; > + pipe_mode->crtc_hsync_start /= 2; > + pipe_mode->crtc_hsync_end /= 2; > + pipe_mode->crtc_htotal /= 2; > + pipe_mode->crtc_hskew /= 2; > + pipe_mode->crtc_clock /= 2; > + } > +} > + > static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) > { > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); > @@ -8461,20 +8548,22 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc, > void intel_mode_from_pipe_config(struct drm_display_mode *mode, > struct intel_crtc_state *pipe_config) > { > - mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay; > - mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal; > - mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start; > - mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end; > + struct drm_display_mode *hw_mode = &pipe_config->hw.adjusted_mode; > + > + mode->hdisplay = hw_mode->crtc_hdisplay; > + mode->htotal = hw_mode->crtc_htotal; > + mode->hsync_start = hw_mode->crtc_hsync_start; > + mode->hsync_end = hw_mode->crtc_hsync_end; > > - mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay; > - mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal; > - mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start; > - mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end; > + mode->vdisplay = hw_mode->crtc_vdisplay; > + mode->vtotal = hw_mode->crtc_vtotal; > + mode->vsync_start = hw_mode->crtc_vsync_start; > + mode->vsync_end = hw_mode->crtc_vsync_end; > > - mode->flags = pipe_config->hw.adjusted_mode.flags; > + mode->flags = hw_mode->flags; > mode->type = DRM_MODE_TYPE_DRIVER; > > - mode->clock = pipe_config->hw.adjusted_mode.crtc_clock; > + mode->clock = hw_mode->crtc_clock; > > mode->hsync = drm_mode_hsync(mode); > mode->vrefresh = drm_mode_vrefresh(mode); > @@ -10564,6 +10653,8 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, > u32 tmp; > > tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); > + if (!(tmp & TRANS_DDI_FUNC_ENABLE)) > + return; > > if (INTEL_GEN(dev_priv) >= 12) > port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp); > @@ -10689,11 +10780,19 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, > WARN_ON(active); > active = true; > } > + intel_dsc_get_config(pipe_config); > > - if (!active) > - goto out; > + if (!active) { > + /* bigjoiner slave doesn't enable transcoder */ > + if (!pipe_config->bigjoiner_slave) > + goto out; > > - if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || > + active = true; > + pipe_config->pixel_multiplier = 1; > + > + /* we cannot read out most state, so don't bother.. */ > + pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE; > + } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || > INTEL_GEN(dev_priv) >= 11) { > haswell_get_ddi_port_state(crtc, pipe_config); > intel_get_transcoder_timings(crtc, pipe_config); > @@ -10770,7 +10869,10 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, > } > } > > - if (pipe_config->cpu_transcoder != TRANSCODER_EDP && > + if (pipe_config->bigjoiner_slave) { > + /* Cannot be read out as a slave, set to 0. */ > + pipe_config->pixel_multiplier = 0; > + } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP && > !transcoder_is_dsi(pipe_config->cpu_transcoder)) { > pipe_config->pixel_multiplier = > I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; > @@ -11748,7 +11850,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder) > return NULL; > } > > - encoder->get_config(encoder, crtc_state); > + intel_encoder_get_config(encoder, crtc_state); > > intel_mode_from_pipe_config(mode, crtc_state); > > @@ -12674,10 +12776,11 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state, > static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state, > struct drm_display_mode *user_mode) > { > - crtc_state->uapi.enable = crtc_state->hw.enable; > - crtc_state->uapi.active = crtc_state->hw.active; > - WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, user_mode) < 0); > - > + if (!crtc_state->bigjoiner_slave) { > + crtc_state->uapi.enable = crtc_state->hw.enable; > + crtc_state->uapi.active = crtc_state->hw.active; > + WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, user_mode) < 0); > + } > crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; > > /* copy color blobs to uapi */ > @@ -13258,21 +13361,43 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > > PIPE_CONF_CHECK_X(output_types); > > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end); > - > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end); > - > - PIPE_CONF_CHECK_I(pixel_multiplier); > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) { > + /* bigjoiner mode = transcoder mode / 2, for calculations */ > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay); > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal); > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay); > + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal); > + > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay); > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal); > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start); > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end); > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start); > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end); > + > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay); > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal); > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start); > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end); > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start); > + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end); > + > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, > + DRM_MODE_FLAG_INTERLACE); > + > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, > + DRM_MODE_FLAG_PHSYNC); > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, > + DRM_MODE_FLAG_NHSYNC); > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, > + DRM_MODE_FLAG_PVSYNC); > + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, > + DRM_MODE_FLAG_NVSYNC); > + } > + PIPE_CONF_CHECK_I(pixel_multiplier); > + } > + > PIPE_CONF_CHECK_I(output_format); > PIPE_CONF_CHECK_I(dc3co_exitline); > PIPE_CONF_CHECK_BOOL(has_hdmi_sink); > @@ -13283,24 +13408,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > PIPE_CONF_CHECK_BOOL(hdmi_scrambling); > PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); > PIPE_CONF_CHECK_BOOL(has_infoframe); > - PIPE_CONF_CHECK_BOOL(fec_enable); > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) > + PIPE_CONF_CHECK_BOOL(fec_enable); > > PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); > > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, > - DRM_MODE_FLAG_INTERLACE); > - > - if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, > - DRM_MODE_FLAG_PHSYNC); > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, > - DRM_MODE_FLAG_NHSYNC); > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, > - DRM_MODE_FLAG_PVSYNC); > - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, > - DRM_MODE_FLAG_NVSYNC); > - } > - > PIPE_CONF_CHECK_X(gmch_pfit.control); > /* pfit ratios are autocomputed by the hw on gen4+ */ > if (INTEL_GEN(dev_priv) < 4) > @@ -13324,7 +13436,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > } > > PIPE_CONF_CHECK_I(scaler_state.scaler_id); > - PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) > + PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); > > PIPE_CONF_CHECK_X(gamma_mode); > if (IS_CHERRYVIEW(dev_priv)) > @@ -13343,48 +13456,51 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > PIPE_CONF_CHECK_BOOL(double_wide); > > PIPE_CONF_CHECK_P(shared_dpll); > + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) { > PIPE_CONF_CHECK_X(dpll_hw_state.dpll); > - PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); > - PIPE_CONF_CHECK_X(dpll_hw_state.fp0); > - PIPE_CONF_CHECK_X(dpll_hw_state.fp1); > - PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); > - PIPE_CONF_CHECK_X(dpll_hw_state.spll); > - PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); > - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); > - PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); > - PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); > - PIPE_CONF_CHECK_X(dpll_hw_state.pll0); > - PIPE_CONF_CHECK_X(dpll_hw_state.pll1); > - PIPE_CONF_CHECK_X(dpll_hw_state.pll2); > - PIPE_CONF_CHECK_X(dpll_hw_state.pll3); > - PIPE_CONF_CHECK_X(dpll_hw_state.pll6); > - PIPE_CONF_CHECK_X(dpll_hw_state.pll8); > - PIPE_CONF_CHECK_X(dpll_hw_state.pll9); > - PIPE_CONF_CHECK_X(dpll_hw_state.pll10); > - PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); > - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); > - > - PIPE_CONF_CHECK_X(dsi_pll.ctrl); > - PIPE_CONF_CHECK_X(dsi_pll.div); > - > - if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) > - PIPE_CONF_CHECK_I(pipe_bpp); > - > - PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); > - PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); > - > - PIPE_CONF_CHECK_I(min_voltage_level); > + PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); > + PIPE_CONF_CHECK_X(dpll_hw_state.fp0); > + PIPE_CONF_CHECK_X(dpll_hw_state.fp1); > + PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); > + PIPE_CONF_CHECK_X(dpll_hw_state.spll); > + PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); > + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); > + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); > + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); > + PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); > + PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll0); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll1); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll2); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll3); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll6); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll8); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll9); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll10); > + PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); > + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); > + > + PIPE_CONF_CHECK_X(dsi_pll.ctrl); > + PIPE_CONF_CHECK_X(dsi_pll.div); > + > + if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) > + PIPE_CONF_CHECK_I(pipe_bpp); > + > + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); > + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); > + PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); > + > + PIPE_CONF_CHECK_I(min_voltage_level); > + } > > PIPE_CONF_CHECK_X(infoframes.enable); > PIPE_CONF_CHECK_X(infoframes.gcp); > @@ -13395,6 +13511,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > > PIPE_CONF_CHECK_I(sync_mode_slaves_mask); > PIPE_CONF_CHECK_I(master_transcoder); > + PIPE_CONF_CHECK_BOOL(bigjoiner); > + PIPE_CONF_CHECK_BOOL(bigjoiner_slave); > + PIPE_CONF_CHECK_P(bigjoiner_linked_crtc); > + PIPE_CONF_CHECK_BOOL(dsc.compression_enable); > + PIPE_CONF_CHECK_BOOL(dsc.dsc_split); > > #undef PIPE_CONF_CHECK_X > #undef PIPE_CONF_CHECK_I > @@ -13650,6 +13771,7 @@ verify_crtc_state(struct intel_crtc *crtc, > struct intel_encoder *encoder; > struct intel_crtc_state *pipe_config; > struct drm_atomic_state *state; > + struct intel_crtc *master = crtc; > bool active; > > state = old_crtc_state->uapi.state; > @@ -13679,7 +13801,10 @@ verify_crtc_state(struct intel_crtc *crtc, > "(expected %i, found %i)\n", > new_crtc_state->hw.active, crtc->active); > > - for_each_encoder_on_crtc(dev, &crtc->base, encoder) { > + if (new_crtc_state->bigjoiner_slave) > + master = new_crtc_state->bigjoiner_linked_crtc; > + > + for_each_encoder_on_crtc(dev, &master->base, encoder) { > enum pipe pipe; > > active = encoder->get_hw_state(encoder, &pipe); > @@ -13688,12 +13813,12 @@ verify_crtc_state(struct intel_crtc *crtc, > encoder->base.base.id, active, > new_crtc_state->hw.active); > > - I915_STATE_WARN(active && crtc->pipe != pipe, > + I915_STATE_WARN(active && master->pipe != pipe, > "Encoder connected to wrong pipe %c\n", > pipe_name(pipe)); > > if (active) > - encoder->get_config(encoder, pipe_config); > + intel_encoder_get_config(encoder, pipe_config); > } > > intel_crtc_compute_pixel_rate(pipe_config); > @@ -14473,7 +14598,6 @@ static void intel_update_crtc(struct intel_crtc *crtc, > > if (modeset) { > intel_crtc_update_active_timings(new_crtc_state); > - > dev_priv->display.crtc_enable(new_crtc_state, state); > > /* vblanks work again, re-enable pipe CRC. */ > @@ -14613,7 +14737,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) > */ > for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state, > new_crtc_state, i) { > - if (!needs_modeset(new_crtc_state)) > + if (!needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner_slave) > continue; > > /* In case of Transcoder port Sync master slave CRTCs can be > @@ -14637,6 +14761,19 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) > old_crtc_state, > new_crtc_state, > crtc); > + > + if (old_crtc_state->bigjoiner) { > + struct intel_crtc *slave = old_crtc_state->bigjoiner_linked_crtc; > + struct intel_crtc_state *old_slave_crtc_state = > + intel_atomic_get_crtc_state(&state->base, slave); > + struct intel_crtc_state *new_slave_crtc_state = > + intel_atomic_get_crtc_state(&state->base, slave); > + > + intel_old_crtc_state_disables(state, > + old_slave_crtc_state, > + new_slave_crtc_state, > + slave); > + } > } > } > } > @@ -17168,7 +17305,7 @@ int intel_modeset_init(struct drm_i915_private *i915) > for_each_intel_crtc(dev, crtc) { > struct intel_initial_plane_config plane_config = {}; > > - if (!crtc->active) > + if (!to_intel_crtc_state(crtc->base.state)->uapi.active) > continue; > > /* > @@ -17624,7 +17761,17 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) > crtc_state = to_intel_crtc_state(crtc->base.state); > > encoder->base.crtc = &crtc->base; > - encoder->get_config(encoder, crtc_state); > + intel_encoder_get_config(encoder, crtc_state); > + > + /* read out to slave crtc as well for bigjoiner */ > + if (crtc_state->bigjoiner) { > + /* encoder should read be linked to bigjoiner master */ > + WARN_ON(crtc_state->bigjoiner_slave); > + > + crtc = crtc_state->bigjoiner_linked_crtc; > + crtc_state = to_intel_crtc_state(crtc->base.state); > + intel_encoder_get_config(encoder, crtc_state); > + } > } else { > encoder->base.crtc = NULL; > } > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index cf2ecfa17416..86a0524b3cd8 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -821,6 +821,7 @@ struct intel_crtc_state { > * accordingly. > */ > #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ > +#define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */ > unsigned long quirks; > > unsigned fb_bits; /* framebuffers to flip */ > @@ -1639,4 +1640,25 @@ static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state) > return i915_ggtt_offset(state->vma); > } > > +static inline bool > +intel_crtc_supports_dsc(const struct intel_crtc_state *pipe_config) > +{ > + struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev); > + > + if (!INTEL_INFO(dev_priv)->display.has_dsc) > + return false; > + > + /* On TGL, DSC is supported on all Pipes */ > + if (INTEL_GEN(dev_priv) >= 12) > + return true; > + > + /* gen10 and gen11 have DSC, but not on pipe A, eDP is allowed */ > + if (INTEL_GEN(dev_priv) >= 10 && > + (to_intel_crtc(pipe_config->uapi.crtc)->pipe != PIPE_A || > + pipe_config->cpu_transcoder == TRANSCODER_EDP)) > + return true; > + > + return false; > +} > + > #endif /* __INTEL_DISPLAY_TYPES_H__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 54fde4c4c4dd..d0b6276f7712 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1948,32 +1948,13 @@ static bool intel_dp_supports_fec(struct intel_dp *intel_dp, > drm_dp_sink_supports_fec(intel_dp->fec_capable); > } > > -static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp, > - const struct intel_crtc_state *pipe_config) > -{ > - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > - > - if (!INTEL_INFO(dev_priv)->display.has_dsc) > - return false; > - > - /* On TGL, DSC is supported on all Pipes */ > - if (INTEL_GEN(dev_priv) >= 12) > - return true; > - > - if (INTEL_GEN(dev_priv) >= 10 && > - pipe_config->cpu_transcoder != TRANSCODER_A) > - return true; > - > - return false; > -} > - > static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, > const struct intel_crtc_state *pipe_config) > { > if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable) > return false; > > - return intel_dp_source_supports_dsc(intel_dp, pipe_config) && > + return intel_crtc_supports_dsc(pipe_config) && > drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); > } > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > index b23ba8d108db..e48608221e71 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -501,11 +501,10 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) > return POWER_DOMAIN_TRANSCODER(cpu_transcoder); > } > > -static void intel_dsc_pps_configure(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state) > +static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; > enum pipe pipe = crtc->pipe; > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > @@ -515,6 +514,9 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; > int i = 0; > > + if (crtc_state->bigjoiner) > + num_vdsc_instances *= 2; > + > /* Populate PICTURE_PARAMETER_SET_0 registers */ > pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << > DSC_VER_MIN_SHIFT | > @@ -920,74 +922,104 @@ static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, > sizeof(dp_dsc_pps_sdp)); > } > > +static i915_reg_t dss_ctl1_reg(const struct intel_crtc_state *crtc_state) > +{ > + enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; > + > + if (crtc_state->cpu_transcoder == TRANSCODER_EDP) > + return DSS_CTL1; > + > + return ICL_PIPE_DSS_CTL1(pipe); > +} > + > +static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state) > +{ > + enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; > + > + if (crtc_state->cpu_transcoder == TRANSCODER_EDP) > + return DSS_CTL2; > + > + return ICL_PIPE_DSS_CTL2(pipe); > +} > + > void intel_dsc_enable(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - enum pipe pipe = crtc->pipe; > - i915_reg_t dss_ctl1_reg, dss_ctl2_reg; > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > u32 dss_ctl1_val = 0; > u32 dss_ctl2_val = 0; > > if (!crtc_state->dsc.compression_enable) > return; > > - /* Enable Power wells for VDSC/joining */ > - intel_display_power_get(dev_priv, > - intel_dsc_power_domain(crtc_state)); > + intel_dsc_pps_configure(crtc_state); > > - intel_dsc_pps_configure(encoder, crtc_state); > + if (!crtc_state->bigjoiner_slave) > + intel_dsc_dp_pps_write(encoder, crtc_state); > > - intel_dsc_dp_pps_write(encoder, crtc_state); > - > - if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { > - dss_ctl1_reg = DSS_CTL1; > - dss_ctl2_reg = DSS_CTL2; > - } else { > - dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); > - dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); > - } > dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; > if (crtc_state->dsc.dsc_split) { > dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; > dss_ctl1_val |= JOINER_ENABLE; > } > - I915_WRITE(dss_ctl1_reg, dss_ctl1_val); > - I915_WRITE(dss_ctl2_reg, dss_ctl2_val); > + if (crtc_state->bigjoiner) { > + dss_ctl1_val |= BIG_JOINER_ENABLE; > + if (!crtc_state->bigjoiner_slave) > + dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE; > + } > + I915_WRITE(dss_ctl1_reg(crtc_state), dss_ctl1_val); > + I915_WRITE(dss_ctl2_reg(crtc_state), dss_ctl2_val); > } > > void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) > { > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > - enum pipe pipe = crtc->pipe; > - i915_reg_t dss_ctl1_reg, dss_ctl2_reg; > - u32 dss_ctl1_val = 0, dss_ctl2_val = 0; > > if (!old_crtc_state->dsc.compression_enable) > return; > > - if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) { > - dss_ctl1_reg = DSS_CTL1; > - dss_ctl2_reg = DSS_CTL2; > - } else { > - dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); > - dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); > + I915_WRITE(dss_ctl1_reg(old_crtc_state), 0); > + I915_WRITE(dss_ctl2_reg(old_crtc_state), 0); > +} > + > +void intel_dsc_get_config(struct intel_crtc_state *crtc_state) > +{ > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + u32 dss_ctl1_val, dss_ctl2_val; > + intel_wakeref_t wakeref; > + > + if (!intel_crtc_supports_dsc(crtc_state)) > + return; > + > + wakeref = intel_display_power_get_if_enabled(dev_priv, intel_dsc_power_domain(crtc_state)); > + if (!wakeref) > + return; > + > + dss_ctl1_val = I915_READ(dss_ctl1_reg(crtc_state)); > + dss_ctl2_val = I915_READ(dss_ctl2_reg(crtc_state)); > + if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE) > + crtc_state->dsc.compression_enable = true; > + > + if ((dss_ctl1_val & JOINER_ENABLE) && (dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)) > + crtc_state->dsc.dsc_split = true; > + > + if (dss_ctl1_val & BIG_JOINER_ENABLE) { > + crtc_state->bigjoiner = true; > + > + if (!(dss_ctl1_val & MASTER_BIG_JOINER_ENABLE)) { > + crtc_state->bigjoiner_slave = true; > + if (!WARN_ON(crtc->pipe == PIPE_A)) > + crtc_state->bigjoiner_linked_crtc = > + intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1); > + } else { > + if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1)) > + crtc_state->bigjoiner_linked_crtc = > + intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1); > + } > } > - dss_ctl1_val = I915_READ(dss_ctl1_reg); > - if (dss_ctl1_val & JOINER_ENABLE) > - dss_ctl1_val &= ~JOINER_ENABLE; > - I915_WRITE(dss_ctl1_reg, dss_ctl1_val); > - > - dss_ctl2_val = I915_READ(dss_ctl2_reg); > - if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE || > - dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE) > - dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE | > - RIGHT_BRANCH_VDSC_ENABLE); > - I915_WRITE(dss_ctl2_reg, dss_ctl2_val); > - > - /* Disable Power wells for VDSC/joining */ > - intel_display_power_put_unchecked(dev_priv, > - intel_dsc_power_domain(old_crtc_state)); > + > + intel_display_power_put(dev_priv, intel_dsc_power_domain(crtc_state), wakeref); > } > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h > index 4ed2256750c3..79d965fedf0b 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.h > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h > @@ -14,6 +14,8 @@ void intel_dsc_enable(struct intel_encoder *encoder, > void intel_dsc_disable(const struct intel_crtc_state *crtc_state); > int intel_dsc_compute_params(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config); > +void intel_dsc_get_config(struct intel_crtc_state *crtc_state); > + > enum intel_display_power_domain > intel_dsc_power_domain(const struct intel_crtc_state *crtc_state); > > -- > 2.24.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Op 28-11-2019 om 20:43 schreef Ville Syrjälä: > On Thu, Nov 14, 2019 at 05:05:17PM +0100, Maarten Lankhorst wrote: >> Make vdsc work when no output is enabled. The big joiner needs VDSC >> on the slave, so enable it and set the appropriate bits. >> Also update timestamping constants, because slave crtc's are not >> updated in drm_atomic_helper_update_legacy_modeset_state(). >> >> This should be enough to bring up CRTC's in a big joiner configuration, >> without any plane configuration on the second pipe yet. >> >> HOWEVER, we still bring up the crtc's in the wrong order. We need to >> make sure that the master crtc is brought up after the slave crtc. >> This is done correctly later in this series. >> >> The next steps are to enable planes correctly, and make sure we enable >> and update both master and slave in the correct order. >> >> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_ddi.c | 48 ++- >> drivers/gpu/drm/i915/display/intel_display.c | 399 ++++++++++++------ >> .../drm/i915/display/intel_display_types.h | 22 + >> drivers/gpu/drm/i915/display/intel_dp.c | 21 +- >> drivers/gpu/drm/i915/display/intel_vdsc.c | 122 ++++-- >> drivers/gpu/drm/i915/display/intel_vdsc.h | 2 + >> 6 files changed, 408 insertions(+), 206 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c >> index 8f817de34460..1215f619da36 100644 >> --- a/drivers/gpu/drm/i915/display/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c >> @@ -2218,13 +2218,6 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, >> intel_phy_is_tc(dev_priv, phy)) >> intel_display_power_get(dev_priv, >> intel_ddi_main_link_aux_domain(dig_port)); >> - >> - /* >> - * VDSC power is needed when DSC is enabled >> - */ >> - if (crtc_state->dsc.compression_enable) >> - intel_display_power_get(dev_priv, >> - intel_dsc_power_domain(crtc_state)); >> } >> >> void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) >> @@ -3557,7 +3550,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, >> >> /* 7.l Configure and enable FEC if needed */ >> intel_ddi_enable_fec(encoder, crtc_state); >> - intel_dsc_enable(encoder, crtc_state); >> + if (!crtc_state->bigjoiner) >> + intel_dsc_enable(encoder, crtc_state); >> } >> >> static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, >> @@ -3629,7 +3623,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, >> if (!is_mst) >> intel_ddi_enable_pipe_clock(crtc_state); >> >> - intel_dsc_enable(encoder, crtc_state); >> + if (!crtc_state->bigjoiner) >> + intel_dsc_enable(encoder, crtc_state); >> } >> >> static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, >> @@ -4252,19 +4247,18 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, >> crtc_state->min_voltage_level = 2; >> } >> >> -void intel_ddi_get_config(struct intel_encoder *encoder, >> - struct intel_crtc_state *pipe_config) >> +static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, >> + struct intel_crtc_state *pipe_config) >> { >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); >> enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; >> u32 temp, flags = 0; >> >> - /* XXX: DSI transcoder paranoia */ >> - if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) >> + temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); >> + if (!(temp & TRANS_DDI_FUNC_ENABLE)) >> return; >> >> - temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); >> if (temp & TRANS_DDI_PHSYNC) >> flags |= DRM_MODE_FLAG_PHSYNC; >> else >> @@ -4350,6 +4344,29 @@ void intel_ddi_get_config(struct intel_encoder *encoder, >> default: >> break; >> } >> +} >> + >> +void intel_ddi_get_config(struct intel_encoder *encoder, >> + struct intel_crtc_state *pipe_config) >> +{ >> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; >> + >> + /* XXX: DSI transcoder paranoia */ >> + if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) >> + return; >> + >> + intel_ddi_read_func_ctl(encoder, pipe_config); >> + if (pipe_config->bigjoiner_slave) { >> + /* read out pipe settings from master */ >> + enum transcoder save = pipe_config->cpu_transcoder; >> + >> + /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */ >> + WARN_ON(pipe_config->output_types); >> + pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe; > That's pretty horrible. > > I don't understand the enable/disable sequence enough to know what > we need to configure/enable where exactly. Bspec just says: > "2. Follow the steps to Enable Planes, Pipe, and Transcoder for pipe C, but > do not configure or enable transcoder C. > 3. Follow the steps to Enable Planes, Pipe, and Transcoder for pipe B and > transcoder B." > > So we need to enable transcoder for pipe C but not enable transcoder C? > I have no idea what actually means. Correct, bspec is slightly unclear here. First we have to bring up the transcoder for pipe B, up to and including enabling FEC. After this, we enable pipe C. None of the transcoder registers for pipe C are ever touched. On pipe C, only the PIPE_* registers are touched, after that we set DSS_CTL1/2 to the correct values for bigjoiner slave mode. After we set up pipe C, we bring up pipe B, continuing from the step after enabling FEC. When immplementing this I was getting a consistent FIFO underrun, but that was because we missed the FEC overhead and it wasn't tested on real hw before. It was fixed in commit cffb4c3ea372 "drm/i915/dp: Fix dsc bpp calculations, v5." After fixing that, the FIFO underrun disappeared and presumably it works on real hardware now, wasn't able to verify on a real DSC monitor. Only on a DSC emulator. :) ~Maarten
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 8f817de34460..1215f619da36 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2218,13 +2218,6 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, intel_phy_is_tc(dev_priv, phy)) intel_display_power_get(dev_priv, intel_ddi_main_link_aux_domain(dig_port)); - - /* - * VDSC power is needed when DSC is enabled - */ - if (crtc_state->dsc.compression_enable) - intel_display_power_get(dev_priv, - intel_dsc_power_domain(crtc_state)); } void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) @@ -3557,7 +3550,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, /* 7.l Configure and enable FEC if needed */ intel_ddi_enable_fec(encoder, crtc_state); - intel_dsc_enable(encoder, crtc_state); + if (!crtc_state->bigjoiner) + intel_dsc_enable(encoder, crtc_state); } static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, @@ -3629,7 +3623,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, if (!is_mst) intel_ddi_enable_pipe_clock(crtc_state); - intel_dsc_enable(encoder, crtc_state); + if (!crtc_state->bigjoiner) + intel_dsc_enable(encoder, crtc_state); } static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, @@ -4252,19 +4247,18 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, crtc_state->min_voltage_level = 2; } -void intel_ddi_get_config(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config) +static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; u32 temp, flags = 0; - /* XXX: DSI transcoder paranoia */ - if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) + temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); + if (!(temp & TRANS_DDI_FUNC_ENABLE)) return; - temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); if (temp & TRANS_DDI_PHSYNC) flags |= DRM_MODE_FLAG_PHSYNC; else @@ -4350,6 +4344,29 @@ void intel_ddi_get_config(struct intel_encoder *encoder, default: break; } +} + +void intel_ddi_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; + + /* XXX: DSI transcoder paranoia */ + if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) + return; + + intel_ddi_read_func_ctl(encoder, pipe_config); + if (pipe_config->bigjoiner_slave) { + /* read out pipe settings from master */ + enum transcoder save = pipe_config->cpu_transcoder; + + /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */ + WARN_ON(pipe_config->output_types); + pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe; + intel_ddi_read_func_ctl(encoder, pipe_config); + pipe_config->cpu_transcoder = save; + } if (encoder->type == INTEL_OUTPUT_EDP) tgl_dc3co_exitline_get_config(pipe_config); @@ -4377,7 +4394,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder, dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; } - intel_ddi_clock_get(encoder, pipe_config); + if (!pipe_config->bigjoiner_slave) + intel_ddi_clock_get(encoder, pipe_config); if (IS_GEN9_LP(dev_priv)) pipe_config->lane_lat_optim_mask = diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 2dc63ef5caf8..94e4cab00a66 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6583,6 +6583,45 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc) I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val); } +static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, + struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_crtc_state *master_crtc_state; + struct drm_connector_state *conn_state; + struct drm_connector *conn; + struct intel_encoder *encoder = NULL; + int i; + + if (crtc_state->bigjoiner_slave) + master = crtc_state->bigjoiner_linked_crtc; + + master_crtc_state = intel_atomic_get_new_crtc_state(state, master); + + for_each_new_connector_in_state(&state->base, conn, conn_state, i) { + if (conn_state->crtc != &master->base) + continue; + + encoder = to_intel_encoder(conn_state->best_encoder); + break; + } + + if (!crtc_state->bigjoiner_slave) { + /* need to enable VDSC, which we skipped in pre-enable */ + intel_dsc_enable(encoder, crtc_state); + } else { + /* + * Enable sequence steps 1-7 on bigjoiner master + */ + intel_encoders_pre_pll_enable(master, master_crtc_state, state); + intel_enable_shared_dpll(master_crtc_state); + intel_encoders_pre_enable(master, master_crtc_state, state); + + /* and DSC on slave */ + intel_dsc_enable(NULL, crtc_state); + } +} + static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, struct intel_atomic_state *state) { @@ -6596,40 +6635,41 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (WARN_ON(intel_crtc->active)) return; - intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state); + if (!pipe_config->bigjoiner) { + intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state); - if (pipe_config->shared_dpll) - intel_enable_shared_dpll(pipe_config); + if (pipe_config->shared_dpll) + intel_enable_shared_dpll(pipe_config); - intel_encoders_pre_enable(intel_crtc, pipe_config, state); + intel_encoders_pre_enable(intel_crtc, pipe_config, state); + } else { + icl_ddi_bigjoiner_pre_enable(state, pipe_config); + } - if (intel_crtc_has_dp_encoder(pipe_config)) - intel_dp_set_m_n(pipe_config, M1_N1); + intel_set_pipe_src_size(pipe_config); + if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) + bdw_set_pipemisc(pipe_config); - if (!transcoder_is_dsi(cpu_transcoder)) - intel_set_transcoder_timings(pipe_config); + if (!pipe_config->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) { + if (intel_crtc_has_dp_encoder(pipe_config)) + intel_dp_set_m_n(pipe_config, M1_N1); - if (INTEL_GEN(dev_priv) >= 11) - icl_enable_trans_port_sync(pipe_config); + if (INTEL_GEN(dev_priv) >= 11) + icl_enable_trans_port_sync(pipe_config); - intel_set_pipe_src_size(pipe_config); + intel_set_transcoder_timings(pipe_config); - if (cpu_transcoder != TRANSCODER_EDP && - !transcoder_is_dsi(cpu_transcoder)) { - I915_WRITE(PIPE_MULT(cpu_transcoder), - pipe_config->pixel_multiplier - 1); - } + if (cpu_transcoder != TRANSCODER_EDP) + I915_WRITE(PIPE_MULT(cpu_transcoder), + pipe_config->pixel_multiplier - 1); - if (pipe_config->has_pch_encoder) { - intel_cpu_transcoder_set_m_n(pipe_config, - &pipe_config->fdi_m_n, NULL); - } + if (pipe_config->has_pch_encoder) { + intel_cpu_transcoder_set_m_n(pipe_config, + &pipe_config->fdi_m_n, NULL); + } - if (!transcoder_is_dsi(cpu_transcoder)) haswell_set_pipeconf(pipe_config); - - if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) - bdw_set_pipemisc(pipe_config); + } intel_crtc->active = true; @@ -6657,7 +6697,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (INTEL_GEN(dev_priv) >= 11) icl_set_pipe_chicken(intel_crtc); - if (!transcoder_is_dsi(cpu_transcoder)) + if (!pipe_config->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) intel_ddi_enable_transcoder_func(pipe_config); if (dev_priv->display.initial_watermarks != NULL) @@ -6667,8 +6707,10 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, icl_pipe_mbus_enable(intel_crtc); /* XXX: Do the pipe assertions at the right place for BXT DSI. */ - if (!transcoder_is_dsi(cpu_transcoder)) + if (!pipe_config->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) intel_enable_pipe(pipe_config); + else + trace_intel_pipe_enable(intel_crtc); if (pipe_config->has_pch_encoder) lpt_pch_enable(state, pipe_config); @@ -6796,9 +6838,27 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, else ironlake_pfit_disable(old_crtc_state); - intel_encoders_post_disable(intel_crtc, old_crtc_state, state); + if (old_crtc_state->bigjoiner) { + struct intel_crtc *master; + struct intel_crtc_state *master_crtc_state; - intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state); + /* ports are disabled from the slave, after it deconfigures */ + if (!old_crtc_state->bigjoiner_slave) + return; + + master = old_crtc_state->bigjoiner_linked_crtc; + master_crtc_state = intel_atomic_get_old_crtc_state(state, master); + + intel_ddi_disable_pipe_clock(old_crtc_state); + + /* disable ports on the master crtc */ + intel_encoders_post_disable(master, master_crtc_state, state); + intel_encoders_post_pll_disable(master, master_crtc_state, state); + } else { + intel_encoders_post_disable(intel_crtc, old_crtc_state, state); + + intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state); + } } static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) @@ -6968,6 +7028,9 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) if (crtc_state->shared_dpll) mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); + if (crtc_state->dsc.compression_enable) + mask |= BIT_ULL(intel_dsc_power_domain(crtc_state)); + return mask; } @@ -7559,6 +7622,30 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) return pixel_rate; } +static void intel_encoder_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; + + encoder->get_config(encoder, crtc_state); + + *pipe_mode = crtc_state->hw.adjusted_mode; + if (crtc_state->bigjoiner) { + /* + * transcoder is programmed to the full mode, + * but pipje timings are half of the transcoder mode + */ + pipe_mode->crtc_hdisplay /= 2; + pipe_mode->crtc_hblank_start /= 2; + pipe_mode->crtc_hblank_end /= 2; + pipe_mode->crtc_hsync_start /= 2; + pipe_mode->crtc_hsync_end /= 2; + pipe_mode->crtc_htotal /= 2; + pipe_mode->crtc_hskew /= 2; + pipe_mode->crtc_clock /= 2; + } +} + static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); @@ -8461,20 +8548,22 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc, void intel_mode_from_pipe_config(struct drm_display_mode *mode, struct intel_crtc_state *pipe_config) { - mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay; - mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal; - mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start; - mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end; + struct drm_display_mode *hw_mode = &pipe_config->hw.adjusted_mode; + + mode->hdisplay = hw_mode->crtc_hdisplay; + mode->htotal = hw_mode->crtc_htotal; + mode->hsync_start = hw_mode->crtc_hsync_start; + mode->hsync_end = hw_mode->crtc_hsync_end; - mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay; - mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal; - mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start; - mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end; + mode->vdisplay = hw_mode->crtc_vdisplay; + mode->vtotal = hw_mode->crtc_vtotal; + mode->vsync_start = hw_mode->crtc_vsync_start; + mode->vsync_end = hw_mode->crtc_vsync_end; - mode->flags = pipe_config->hw.adjusted_mode.flags; + mode->flags = hw_mode->flags; mode->type = DRM_MODE_TYPE_DRIVER; - mode->clock = pipe_config->hw.adjusted_mode.crtc_clock; + mode->clock = hw_mode->crtc_clock; mode->hsync = drm_mode_hsync(mode); mode->vrefresh = drm_mode_vrefresh(mode); @@ -10564,6 +10653,8 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, u32 tmp; tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); + if (!(tmp & TRANS_DDI_FUNC_ENABLE)) + return; if (INTEL_GEN(dev_priv) >= 12) port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp); @@ -10689,11 +10780,19 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, WARN_ON(active); active = true; } + intel_dsc_get_config(pipe_config); - if (!active) - goto out; + if (!active) { + /* bigjoiner slave doesn't enable transcoder */ + if (!pipe_config->bigjoiner_slave) + goto out; - if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || + active = true; + pipe_config->pixel_multiplier = 1; + + /* we cannot read out most state, so don't bother.. */ + pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE; + } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || INTEL_GEN(dev_priv) >= 11) { haswell_get_ddi_port_state(crtc, pipe_config); intel_get_transcoder_timings(crtc, pipe_config); @@ -10770,7 +10869,10 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, } } - if (pipe_config->cpu_transcoder != TRANSCODER_EDP && + if (pipe_config->bigjoiner_slave) { + /* Cannot be read out as a slave, set to 0. */ + pipe_config->pixel_multiplier = 0; + } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP && !transcoder_is_dsi(pipe_config->cpu_transcoder)) { pipe_config->pixel_multiplier = I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; @@ -11748,7 +11850,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder) return NULL; } - encoder->get_config(encoder, crtc_state); + intel_encoder_get_config(encoder, crtc_state); intel_mode_from_pipe_config(mode, crtc_state); @@ -12674,10 +12776,11 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state, static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state, struct drm_display_mode *user_mode) { - crtc_state->uapi.enable = crtc_state->hw.enable; - crtc_state->uapi.active = crtc_state->hw.active; - WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, user_mode) < 0); - + if (!crtc_state->bigjoiner_slave) { + crtc_state->uapi.enable = crtc_state->hw.enable; + crtc_state->uapi.active = crtc_state->hw.active; + WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, user_mode) < 0); + } crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; /* copy color blobs to uapi */ @@ -13258,21 +13361,43 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_X(output_types); - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay); - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal); - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start); - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end); - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start); - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end); - - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay); - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal); - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start); - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end); - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start); - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end); - - PIPE_CONF_CHECK_I(pixel_multiplier); + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) { + /* bigjoiner mode = transcoder mode / 2, for calculations */ + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay); + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal); + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay); + PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal); + + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay); + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal); + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start); + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end); + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start); + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end); + + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay); + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal); + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start); + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end); + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start); + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end); + + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, + DRM_MODE_FLAG_INTERLACE); + + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, + DRM_MODE_FLAG_PHSYNC); + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, + DRM_MODE_FLAG_NHSYNC); + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, + DRM_MODE_FLAG_PVSYNC); + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, + DRM_MODE_FLAG_NVSYNC); + } + PIPE_CONF_CHECK_I(pixel_multiplier); + } + PIPE_CONF_CHECK_I(output_format); PIPE_CONF_CHECK_I(dc3co_exitline); PIPE_CONF_CHECK_BOOL(has_hdmi_sink); @@ -13283,24 +13408,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(hdmi_scrambling); PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); PIPE_CONF_CHECK_BOOL(has_infoframe); - PIPE_CONF_CHECK_BOOL(fec_enable); + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) + PIPE_CONF_CHECK_BOOL(fec_enable); PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, - DRM_MODE_FLAG_INTERLACE); - - if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, - DRM_MODE_FLAG_PHSYNC); - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, - DRM_MODE_FLAG_NHSYNC); - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, - DRM_MODE_FLAG_PVSYNC); - PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, - DRM_MODE_FLAG_NVSYNC); - } - PIPE_CONF_CHECK_X(gmch_pfit.control); /* pfit ratios are autocomputed by the hw on gen4+ */ if (INTEL_GEN(dev_priv) < 4) @@ -13324,7 +13436,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, } PIPE_CONF_CHECK_I(scaler_state.scaler_id); - PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) + PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); PIPE_CONF_CHECK_X(gamma_mode); if (IS_CHERRYVIEW(dev_priv)) @@ -13343,48 +13456,51 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(double_wide); PIPE_CONF_CHECK_P(shared_dpll); + if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) { PIPE_CONF_CHECK_X(dpll_hw_state.dpll); - PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); - PIPE_CONF_CHECK_X(dpll_hw_state.fp0); - PIPE_CONF_CHECK_X(dpll_hw_state.fp1); - PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); - PIPE_CONF_CHECK_X(dpll_hw_state.spll); - PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); - PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); - PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); - PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); - PIPE_CONF_CHECK_X(dpll_hw_state.pll0); - PIPE_CONF_CHECK_X(dpll_hw_state.pll1); - PIPE_CONF_CHECK_X(dpll_hw_state.pll2); - PIPE_CONF_CHECK_X(dpll_hw_state.pll3); - PIPE_CONF_CHECK_X(dpll_hw_state.pll6); - PIPE_CONF_CHECK_X(dpll_hw_state.pll8); - PIPE_CONF_CHECK_X(dpll_hw_state.pll9); - PIPE_CONF_CHECK_X(dpll_hw_state.pll10); - PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); - PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); - PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); - PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); - - PIPE_CONF_CHECK_X(dsi_pll.ctrl); - PIPE_CONF_CHECK_X(dsi_pll.div); - - if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) - PIPE_CONF_CHECK_I(pipe_bpp); - - PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); - PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); - - PIPE_CONF_CHECK_I(min_voltage_level); + PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); + PIPE_CONF_CHECK_X(dpll_hw_state.fp0); + PIPE_CONF_CHECK_X(dpll_hw_state.fp1); + PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); + PIPE_CONF_CHECK_X(dpll_hw_state.spll); + PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); + PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); + PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); + PIPE_CONF_CHECK_X(dpll_hw_state.pll0); + PIPE_CONF_CHECK_X(dpll_hw_state.pll1); + PIPE_CONF_CHECK_X(dpll_hw_state.pll2); + PIPE_CONF_CHECK_X(dpll_hw_state.pll3); + PIPE_CONF_CHECK_X(dpll_hw_state.pll6); + PIPE_CONF_CHECK_X(dpll_hw_state.pll8); + PIPE_CONF_CHECK_X(dpll_hw_state.pll9); + PIPE_CONF_CHECK_X(dpll_hw_state.pll10); + PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); + PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); + PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); + PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); + PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); + + PIPE_CONF_CHECK_X(dsi_pll.ctrl); + PIPE_CONF_CHECK_X(dsi_pll.div); + + if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) + PIPE_CONF_CHECK_I(pipe_bpp); + + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); + PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); + + PIPE_CONF_CHECK_I(min_voltage_level); + } PIPE_CONF_CHECK_X(infoframes.enable); PIPE_CONF_CHECK_X(infoframes.gcp); @@ -13395,6 +13511,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(sync_mode_slaves_mask); PIPE_CONF_CHECK_I(master_transcoder); + PIPE_CONF_CHECK_BOOL(bigjoiner); + PIPE_CONF_CHECK_BOOL(bigjoiner_slave); + PIPE_CONF_CHECK_P(bigjoiner_linked_crtc); + PIPE_CONF_CHECK_BOOL(dsc.compression_enable); + PIPE_CONF_CHECK_BOOL(dsc.dsc_split); #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I @@ -13650,6 +13771,7 @@ verify_crtc_state(struct intel_crtc *crtc, struct intel_encoder *encoder; struct intel_crtc_state *pipe_config; struct drm_atomic_state *state; + struct intel_crtc *master = crtc; bool active; state = old_crtc_state->uapi.state; @@ -13679,7 +13801,10 @@ verify_crtc_state(struct intel_crtc *crtc, "(expected %i, found %i)\n", new_crtc_state->hw.active, crtc->active); - for_each_encoder_on_crtc(dev, &crtc->base, encoder) { + if (new_crtc_state->bigjoiner_slave) + master = new_crtc_state->bigjoiner_linked_crtc; + + for_each_encoder_on_crtc(dev, &master->base, encoder) { enum pipe pipe; active = encoder->get_hw_state(encoder, &pipe); @@ -13688,12 +13813,12 @@ verify_crtc_state(struct intel_crtc *crtc, encoder->base.base.id, active, new_crtc_state->hw.active); - I915_STATE_WARN(active && crtc->pipe != pipe, + I915_STATE_WARN(active && master->pipe != pipe, "Encoder connected to wrong pipe %c\n", pipe_name(pipe)); if (active) - encoder->get_config(encoder, pipe_config); + intel_encoder_get_config(encoder, pipe_config); } intel_crtc_compute_pixel_rate(pipe_config); @@ -14473,7 +14598,6 @@ static void intel_update_crtc(struct intel_crtc *crtc, if (modeset) { intel_crtc_update_active_timings(new_crtc_state); - dev_priv->display.crtc_enable(new_crtc_state, state); /* vblanks work again, re-enable pipe CRC. */ @@ -14613,7 +14737,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) */ for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state, new_crtc_state, i) { - if (!needs_modeset(new_crtc_state)) + if (!needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner_slave) continue; /* In case of Transcoder port Sync master slave CRTCs can be @@ -14637,6 +14761,19 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) old_crtc_state, new_crtc_state, crtc); + + if (old_crtc_state->bigjoiner) { + struct intel_crtc *slave = old_crtc_state->bigjoiner_linked_crtc; + struct intel_crtc_state *old_slave_crtc_state = + intel_atomic_get_crtc_state(&state->base, slave); + struct intel_crtc_state *new_slave_crtc_state = + intel_atomic_get_crtc_state(&state->base, slave); + + intel_old_crtc_state_disables(state, + old_slave_crtc_state, + new_slave_crtc_state, + slave); + } } } } @@ -17168,7 +17305,7 @@ int intel_modeset_init(struct drm_i915_private *i915) for_each_intel_crtc(dev, crtc) { struct intel_initial_plane_config plane_config = {}; - if (!crtc->active) + if (!to_intel_crtc_state(crtc->base.state)->uapi.active) continue; /* @@ -17624,7 +17761,17 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) crtc_state = to_intel_crtc_state(crtc->base.state); encoder->base.crtc = &crtc->base; - encoder->get_config(encoder, crtc_state); + intel_encoder_get_config(encoder, crtc_state); + + /* read out to slave crtc as well for bigjoiner */ + if (crtc_state->bigjoiner) { + /* encoder should read be linked to bigjoiner master */ + WARN_ON(crtc_state->bigjoiner_slave); + + crtc = crtc_state->bigjoiner_linked_crtc; + crtc_state = to_intel_crtc_state(crtc->base.state); + intel_encoder_get_config(encoder, crtc_state); + } } else { encoder->base.crtc = NULL; } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index cf2ecfa17416..86a0524b3cd8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -821,6 +821,7 @@ struct intel_crtc_state { * accordingly. */ #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ +#define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */ unsigned long quirks; unsigned fb_bits; /* framebuffers to flip */ @@ -1639,4 +1640,25 @@ static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state) return i915_ggtt_offset(state->vma); } +static inline bool +intel_crtc_supports_dsc(const struct intel_crtc_state *pipe_config) +{ + struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev); + + if (!INTEL_INFO(dev_priv)->display.has_dsc) + return false; + + /* On TGL, DSC is supported on all Pipes */ + if (INTEL_GEN(dev_priv) >= 12) + return true; + + /* gen10 and gen11 have DSC, but not on pipe A, eDP is allowed */ + if (INTEL_GEN(dev_priv) >= 10 && + (to_intel_crtc(pipe_config->uapi.crtc)->pipe != PIPE_A || + pipe_config->cpu_transcoder == TRANSCODER_EDP)) + return true; + + return false; +} + #endif /* __INTEL_DISPLAY_TYPES_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 54fde4c4c4dd..d0b6276f7712 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1948,32 +1948,13 @@ static bool intel_dp_supports_fec(struct intel_dp *intel_dp, drm_dp_sink_supports_fec(intel_dp->fec_capable); } -static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp, - const struct intel_crtc_state *pipe_config) -{ - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - - if (!INTEL_INFO(dev_priv)->display.has_dsc) - return false; - - /* On TGL, DSC is supported on all Pipes */ - if (INTEL_GEN(dev_priv) >= 12) - return true; - - if (INTEL_GEN(dev_priv) >= 10 && - pipe_config->cpu_transcoder != TRANSCODER_A) - return true; - - return false; -} - static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, const struct intel_crtc_state *pipe_config) { if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable) return false; - return intel_dp_source_supports_dsc(intel_dp, pipe_config) && + return intel_crtc_supports_dsc(pipe_config) && drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); } diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index b23ba8d108db..e48608221e71 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -501,11 +501,10 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) return POWER_DOMAIN_TRANSCODER(cpu_transcoder); } -static void intel_dsc_pps_configure(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; enum pipe pipe = crtc->pipe; enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; @@ -515,6 +514,9 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; int i = 0; + if (crtc_state->bigjoiner) + num_vdsc_instances *= 2; + /* Populate PICTURE_PARAMETER_SET_0 registers */ pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << DSC_VER_MIN_SHIFT | @@ -920,74 +922,104 @@ static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, sizeof(dp_dsc_pps_sdp)); } +static i915_reg_t dss_ctl1_reg(const struct intel_crtc_state *crtc_state) +{ + enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; + + if (crtc_state->cpu_transcoder == TRANSCODER_EDP) + return DSS_CTL1; + + return ICL_PIPE_DSS_CTL1(pipe); +} + +static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state) +{ + enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; + + if (crtc_state->cpu_transcoder == TRANSCODER_EDP) + return DSS_CTL2; + + return ICL_PIPE_DSS_CTL2(pipe); +} + void intel_dsc_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum pipe pipe = crtc->pipe; - i915_reg_t dss_ctl1_reg, dss_ctl2_reg; + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dss_ctl1_val = 0; u32 dss_ctl2_val = 0; if (!crtc_state->dsc.compression_enable) return; - /* Enable Power wells for VDSC/joining */ - intel_display_power_get(dev_priv, - intel_dsc_power_domain(crtc_state)); + intel_dsc_pps_configure(crtc_state); - intel_dsc_pps_configure(encoder, crtc_state); + if (!crtc_state->bigjoiner_slave) + intel_dsc_dp_pps_write(encoder, crtc_state); - intel_dsc_dp_pps_write(encoder, crtc_state); - - if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { - dss_ctl1_reg = DSS_CTL1; - dss_ctl2_reg = DSS_CTL2; - } else { - dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); - dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); - } dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; if (crtc_state->dsc.dsc_split) { dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; dss_ctl1_val |= JOINER_ENABLE; } - I915_WRITE(dss_ctl1_reg, dss_ctl1_val); - I915_WRITE(dss_ctl2_reg, dss_ctl2_val); + if (crtc_state->bigjoiner) { + dss_ctl1_val |= BIG_JOINER_ENABLE; + if (!crtc_state->bigjoiner_slave) + dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE; + } + I915_WRITE(dss_ctl1_reg(crtc_state), dss_ctl1_val); + I915_WRITE(dss_ctl2_reg(crtc_state), dss_ctl2_val); } void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) { struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum pipe pipe = crtc->pipe; - i915_reg_t dss_ctl1_reg, dss_ctl2_reg; - u32 dss_ctl1_val = 0, dss_ctl2_val = 0; if (!old_crtc_state->dsc.compression_enable) return; - if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) { - dss_ctl1_reg = DSS_CTL1; - dss_ctl2_reg = DSS_CTL2; - } else { - dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); - dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); + I915_WRITE(dss_ctl1_reg(old_crtc_state), 0); + I915_WRITE(dss_ctl2_reg(old_crtc_state), 0); +} + +void intel_dsc_get_config(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + u32 dss_ctl1_val, dss_ctl2_val; + intel_wakeref_t wakeref; + + if (!intel_crtc_supports_dsc(crtc_state)) + return; + + wakeref = intel_display_power_get_if_enabled(dev_priv, intel_dsc_power_domain(crtc_state)); + if (!wakeref) + return; + + dss_ctl1_val = I915_READ(dss_ctl1_reg(crtc_state)); + dss_ctl2_val = I915_READ(dss_ctl2_reg(crtc_state)); + if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE) + crtc_state->dsc.compression_enable = true; + + if ((dss_ctl1_val & JOINER_ENABLE) && (dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)) + crtc_state->dsc.dsc_split = true; + + if (dss_ctl1_val & BIG_JOINER_ENABLE) { + crtc_state->bigjoiner = true; + + if (!(dss_ctl1_val & MASTER_BIG_JOINER_ENABLE)) { + crtc_state->bigjoiner_slave = true; + if (!WARN_ON(crtc->pipe == PIPE_A)) + crtc_state->bigjoiner_linked_crtc = + intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1); + } else { + if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1)) + crtc_state->bigjoiner_linked_crtc = + intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1); + } } - dss_ctl1_val = I915_READ(dss_ctl1_reg); - if (dss_ctl1_val & JOINER_ENABLE) - dss_ctl1_val &= ~JOINER_ENABLE; - I915_WRITE(dss_ctl1_reg, dss_ctl1_val); - - dss_ctl2_val = I915_READ(dss_ctl2_reg); - if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE || - dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE) - dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE | - RIGHT_BRANCH_VDSC_ENABLE); - I915_WRITE(dss_ctl2_reg, dss_ctl2_val); - - /* Disable Power wells for VDSC/joining */ - intel_display_power_put_unchecked(dev_priv, - intel_dsc_power_domain(old_crtc_state)); + + intel_display_power_put(dev_priv, intel_dsc_power_domain(crtc_state), wakeref); } diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h index 4ed2256750c3..79d965fedf0b 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h @@ -14,6 +14,8 @@ void intel_dsc_enable(struct intel_encoder *encoder, void intel_dsc_disable(const struct intel_crtc_state *crtc_state); int intel_dsc_compute_params(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config); +void intel_dsc_get_config(struct intel_crtc_state *crtc_state); + enum intel_display_power_domain intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
Make vdsc work when no output is enabled. The big joiner needs VDSC on the slave, so enable it and set the appropriate bits. Also update timestamping constants, because slave crtc's are not updated in drm_atomic_helper_update_legacy_modeset_state(). This should be enough to bring up CRTC's in a big joiner configuration, without any plane configuration on the second pipe yet. HOWEVER, we still bring up the crtc's in the wrong order. We need to make sure that the master crtc is brought up after the slave crtc. This is done correctly later in this series. The next steps are to enable planes correctly, and make sure we enable and update both master and slave in the correct order. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 48 ++- drivers/gpu/drm/i915/display/intel_display.c | 399 ++++++++++++------ .../drm/i915/display/intel_display_types.h | 22 + drivers/gpu/drm/i915/display/intel_dp.c | 21 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 122 ++++-- drivers/gpu/drm/i915/display/intel_vdsc.h | 2 + 6 files changed, 408 insertions(+), 206 deletions(-)