From patchwork Tue Dec 3 17:36:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 11271763 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D4DAC139A for ; Tue, 3 Dec 2019 17:37:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BA90D206EC for ; Tue, 3 Dec 2019 17:37:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BA90D206EC Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=poorly.run Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8FD2C6EA3F; Tue, 3 Dec 2019 17:37:14 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yw1-xc44.google.com (mail-yw1-xc44.google.com [IPv6:2607:f8b0:4864:20::c44]) by gabe.freedesktop.org (Postfix) with ESMTPS id A4EEA6EA3B for ; Tue, 3 Dec 2019 17:37:12 +0000 (UTC) Received: by mail-yw1-xc44.google.com with SMTP id u139so1615171ywf.13 for ; Tue, 03 Dec 2019 09:37:12 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5RS+iM/8Pmfn6MpQu7z1NjYnwPdtK2Ar3CetwZVrW2g=; b=Flb5YawQkON1mlHJfkpvF9xGuqlUCQNKVr0geU6lbn5zzsOT6gbzwO9OkbyA4QrVmE ShmKpe4x4SDRDKp+7XH4ytYfl+GQZgr30V4DSaZBk4iLiJWKT1wHpuzBMApew9YayRXd x4YftMCj97wZFOQ2590ipXcI5124o+BwnvCvrVAaSwjQ5fdpL6d0N3Yzy3/8U0bubIBx OMYsX+Ritbp2NwYfwY4Vdc5bU5UD9YNABA13tbaoPriipCH8HyTnkhBXZ7KtaRM0XpIl o7ZRfURU2KBNtWrXBLOhddgrQb1hly44u0pHVDXiXLTu8QHHZ6nv/aEG9PADq4DX6OOu i2lw== X-Gm-Message-State: APjAAAWgU9LezSenIdPKsNlTe1hjTcXy4tPArzIs3ySvlMy/L2IwM9MA Qlb3Asi4YdmuW4XFoYb8Yh+3Dw== X-Google-Smtp-Source: APXvYqy6hNUL7CTqpboW/YMRNd11R7bjZGZhsCjUK3Lmf1H/sFSH/bqlZtRf4fJLBnU6sGxoiT76gw== X-Received: by 2002:a81:4bd1:: with SMTP id y200mr4983901ywa.94.1575394631862; Tue, 03 Dec 2019 09:37:11 -0800 (PST) Received: from rosewood.cam.corp.google.com ([2620:0:1013:11:89c6:2139:5435:371d]) by smtp.gmail.com with ESMTPSA id g190sm1729426ywf.41.2019.12.03.09.37.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 09:37:11 -0800 (PST) From: Sean Paul To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, ramalingm.c@intel.com Date: Tue, 3 Dec 2019 12:36:26 -0500 Message-Id: <20191203173638.94919-4-sean@poorly.run> X-Mailer: git-send-email 2.24.0.393.g34dc348eaf-goog In-Reply-To: <20191203173638.94919-1-sean@poorly.run> References: <20191203173638.94919-1-sean@poorly.run> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=poorly.run; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5RS+iM/8Pmfn6MpQu7z1NjYnwPdtK2Ar3CetwZVrW2g=; b=FRUmH04bVZo7IFI3jxMpLzrJ643A59AfWyQ6Z6zHqAlMxHtWf9NdhM9Ycd8w3tOKTb 8Yk4/4KMfFECAUCg5GDJ4sfJHinyXCCpp+iW/I/OjZpnNsbLnHj523ya4DJhuqfp9nCn /6ufaeOzMYiDVNL/wdbYoLXs216xCUdGDOUArQmkrEIdj4/MngnXZvbw3lneaihpWu25 YZ09tjHt1dzRmhX3FbdXVWmsSmdrAatDXxUWlZldFMtcM8PA1X78XJdxcfYPD+U14K5u 35seMN8J7eiqHTyltWfFHbwOleV+01vMrONfYu44h7CEv3FcuSjoUYxEQnnZDXgJmpwQ uuPA== Subject: [Intel-gfx] [PATCH 03/11] drm/i915: Disable HDCP signalling on transcoder disable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , Sean Paul Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Sean Paul Currently we rely on intel_hdcp_disable() to disable HDCP signalling in the DDI Function Control register. This patch adds a safety net by also clearing the bit when we disable the transcoder. Once we have HDCP over MST and disappearing connectors, we want to make sure that the signalling is truly disabled even if HDCP teardown doesn't go as planned. Signed-off-by: Sean Paul --- drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index b51f244ad7a5..e8ac98a8ee7f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1952,13 +1952,12 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); u32 val = I915_READ(reg); - if (INTEL_GEN(dev_priv) >= 12) { - val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK | - TRANS_DDI_DP_VC_PAYLOAD_ALLOC); - } else { - val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | - TRANS_DDI_DP_VC_PAYLOAD_ALLOC); - } + val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_DP_VC_PAYLOAD_ALLOC | + TRANS_DDI_HDCP_SIGNALLING); + if (INTEL_GEN(dev_priv) >= 12) + val &= ~TGL_TRANS_DDI_PORT_MASK; + else + val &= ~TRANS_DDI_PORT_MASK; I915_WRITE(reg, val); if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&