From patchwork Mon Dec 9 21:39:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11280463 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5FE94930 for ; Mon, 9 Dec 2019 21:39:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 48BFD205C9 for ; Mon, 9 Dec 2019 21:39:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 48BFD205C9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 884A26E529; Mon, 9 Dec 2019 21:39:14 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8A8166E529 for ; Mon, 9 Dec 2019 21:39:13 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Dec 2019 13:39:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,296,1571727600"; d="scan'208";a="207042512" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga008.jf.intel.com with SMTP; 09 Dec 2019 13:39:10 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 09 Dec 2019 23:39:09 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Mon, 9 Dec 2019 23:39:09 +0200 Message-Id: <20191209213909.5402-1-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915: Implement pps w/a #1124 for bxt+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The panel power sequencer can get confused if we follow a PP_ON_DELAYS write with a PP_CONTROL power state target write. Apparently it can latch the old PP_ON_DELAYS value instead of the new one. Instead of mucking about with clock gating disables until we enable the power sequencer let's just do the trivial 100us+ delay. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0f496115c345..9cb2ec91039f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6876,6 +6876,17 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, } else { u32 pp_ctl; + /* + * Display WA #1124: bxt,glk,cnl + * "WA: Wait at least 100us between programming + * PP_ON_DELAYS and enabling Power State Target in + * PP_CONTROL, or disable dpls clock gating before + * programming PP_ON_DELAYS and leave disabled until + * after enabling Power State Target in PP_CONTROL." + */ + if (INTEL_GEN(dev_priv) < 11) + usleep_range(100, 200); + pp_ctl = I915_READ(regs.pp_ctrl); pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK; pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));