From patchwork Wed Dec 11 02:08:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11283741 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EB09213B6 for ; Wed, 11 Dec 2019 02:09:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D39CC20652 for ; Wed, 11 Dec 2019 02:09:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D39CC20652 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 018F86EA46; Wed, 11 Dec 2019 02:09:06 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id AA97D6EA38 for ; Wed, 11 Dec 2019 02:09:02 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Dec 2019 18:09:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,301,1571727600"; d="scan'208";a="210618390" Received: from josouza-mobl.jf.intel.com (HELO josouza-MOBL.intel.com) ([10.98.40.69]) by fmsmga008.fm.intel.com with ESMTP; 10 Dec 2019 18:09:01 -0800 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 10 Dec 2019 18:08:55 -0800 Message-Id: <20191211020858.423049-8-jose.souza@intel.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191211020858.423049-1-jose.souza@intel.com> References: <20191211020858.423049-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 08/11] drm/i915/display: Always enables MST master pipe first X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Due to DDB overlaps the pipe enabling sequence is not always crescent. As the previous patch selects the smallest pipe/transcoder in the MST stream to be master and it needs to be enabled first this changes were needed to guarantee that. So first lets enable all pipes that did not needed a fullmodeset so it don't have any external dependency, this ones can overlap with each other ddb allocations. Then on the second loop it will enable all the pipes that needs a modeset and don't depends on other pipes like MST master pipe/transcoder. Then finally all the pipes that needs a modeset and have dependency on other pipes. Cc: Ville Syrjälä Cc: Maarten Lankhorst Cc: Matt Roper Cc: Manasi Navare Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 77 ++++++++++++++------ 1 file changed, 56 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index d059948eec9a..6a815c11c83c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14566,18 +14566,24 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) /* * Whenever the number of active pipes changes, we need to make sure we * update the pipes in the right order so that their ddb allocations - * never overlap with eachother inbetween CRTC updates. Otherwise we'll + * never overlap with each other between CRTC updates. Otherwise we'll * cause pipe underruns and other bad stuff. + * + * So first lets enable all pipes that did not needed a fullmodeset so + * it don't have any external dependency */ do { progress = false; - for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { - enum pipe pipe = crtc->pipe; - bool vbl_wait = false; - bool modeset = needs_modeset(new_crtc_state); + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + bool vbl_wait; + + if (updated & BIT(crtc->pipe) || + !new_crtc_state->hw.active) + continue; - if (updated & BIT(crtc->pipe) || !new_crtc_state->hw.active) + if (needs_modeset(new_crtc_state)) continue; if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, @@ -14585,7 +14591,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) INTEL_NUM_PIPES(dev_priv), i)) continue; - updated |= BIT(pipe); + updated |= BIT(crtc->pipe); entries[i] = new_crtc_state->wm.skl.ddb; /* @@ -14596,30 +14602,59 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) */ if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, &old_crtc_state->wm.skl.ddb) && - !modeset && state->wm_results.dirty_pipes != updated) vbl_wait = true; - if (modeset && is_trans_port_sync_mode(new_crtc_state)) { - if (is_trans_port_sync_master(new_crtc_state)) - intel_update_trans_port_sync_crtcs(crtc, - state, - old_crtc_state, - new_crtc_state); - else - continue; - } else { - intel_update_crtc(crtc, state, old_crtc_state, - new_crtc_state); - } + intel_update_crtc(crtc, state, old_crtc_state, + new_crtc_state); if (vbl_wait) - intel_wait_for_vblank(dev_priv, pipe); + intel_wait_for_vblank(dev_priv, crtc->pipe); progress = true; } } while (progress); + /* + * Enabling all pipes that needs a modeset and do not depends on other + * pipes + */ + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + if (updated & BIT(crtc->pipe) || !new_crtc_state->hw.active) + continue; + + if (intel_dp_mst_is_slave_trans(new_crtc_state) || + is_trans_port_sync_slave(new_crtc_state)) + continue; + + updated |= BIT(crtc->pipe); + + if (is_trans_port_sync_mode(new_crtc_state)) + intel_update_trans_port_sync_crtcs(crtc, state, + old_crtc_state, + new_crtc_state); + else + intel_update_crtc(crtc, state, old_crtc_state, + new_crtc_state); + } + + /* + * Finally enable all pipes that needs a modeset and depends on + * other pipes, right now it is only MST slaves as both port sync slave + * and master are enabled together + */ + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + if (updated & BIT(crtc->pipe) || !new_crtc_state->hw.active) + continue; + + if (is_trans_port_sync_slave(new_crtc_state)) + continue; + + intel_update_crtc(crtc, state, old_crtc_state, new_crtc_state); + } + /* If 2nd DBuf slice is no more required disable it */ if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices) icl_dbuf_slices_update(dev_priv, required_slices);