diff mbox series

[03/33] drm/i915/gt: Eliminate the trylock for reading a timeline's hwsp

Message ID 20191212140459.1307617-3-chris@chris-wilson.co.uk (mailing list archive)
State New, archived
Headers show
Series [01/33] drm/i915: Use EAGAIN for trylock failures | expand

Commit Message

Chris Wilson Dec. 12, 2019, 2:04 p.m. UTC 
As we stash a pointer to the HWSP cacheline on the request, when reading
it we only need confirm that the cacheline is still valid by checking
that the request and timeline are still intact.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_timeline.c | 38 ++++++++----------------
 1 file changed, 13 insertions(+), 25 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
index d71aafb66d6e..e852bd142ddf 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -514,6 +514,7 @@  int intel_timeline_read_hwsp(struct i915_request *from,
 			     struct i915_request *to,
 			     u32 *hwsp)
 {
+	struct intel_timeline_cacheline *cl = from->hwsp_cacheline;
 	struct intel_timeline *tl;
 	int err;
 
@@ -526,33 +527,20 @@  int intel_timeline_read_hwsp(struct i915_request *from,
 		return 1;
 
 	GEM_BUG_ON(rcu_access_pointer(to->timeline) == tl);
-
-	err = -EAGAIN;
-	if (mutex_trylock(&tl->mutex)) {
-		struct intel_timeline_cacheline *cl = from->hwsp_cacheline;
-
-		if (i915_request_completed(from)) {
-			err = 1;
-			goto unlock;
-		}
-
-		err = cacheline_ref(cl, to);
-		if (err)
-			goto unlock;
-
-		if (likely(cl == tl->hwsp_cacheline)) {
-			*hwsp = tl->hwsp_offset;
-		} else { /* across a seqno wrap, recover the original offset */
-			*hwsp = i915_ggtt_offset(cl->hwsp->vma) +
-				ptr_unmask_bits(cl->vaddr, CACHELINE_BITS) *
-				CACHELINE_BYTES;
-		}
-
-unlock:
-		mutex_unlock(&tl->mutex);
+	err = cacheline_ref(cl, to);
+	if (err)
+		goto out;
+
+	*hwsp = tl->hwsp_offset;
+	if (unlikely(cl != READ_ONCE(tl->hwsp_cacheline))) {
+		/* across a seqno wrap, recover the original offset */
+		*hwsp = i915_ggtt_offset(cl->hwsp->vma) +
+			ptr_unmask_bits(cl->vaddr, CACHELINE_BITS) *
+			CACHELINE_BYTES;
 	}
-	intel_timeline_put(tl);
 
+out:
+	intel_timeline_put(tl);
 	return err;
 }