| Message ID | 20191218161105.30638-12-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/tgl: Render/media decompression support | expand |
On Wed, 2019-12-18 at 18:11 +0200, Imre Deak wrote: > From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Gen-12 display can decompress surfaces compressed by the media > engine, add > a new modifier as the driver needs to know the surface was compressed > by > the media or render engine. > > v2: Update code comment describing the color plane order for YUV > semiplanar formats. > > Cc: Nanley G Chery <nanley.g.chery@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> > --- > include/uapi/drm/drm_fourcc.h | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/include/uapi/drm/drm_fourcc.h > b/include/uapi/drm/drm_fourcc.h > index 5ba481f49931..8bc0b31597d8 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -421,6 +421,19 @@ extern "C" { > */ > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, > 6) > > +/* > + * Intel color control surfaces (CCS) for Gen-12 media compression > + * > + * The main surface is Y-tiled and at plane index 0, the CCS is > linear and > + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 > tiles in > + * main surface. In other words, 4 bits in CCS map to a main surface > cache > + * line pair. The main surface pitch is required to be a multiple of > four > + * Y-tile widths. For semi-planar formats like NV12, CCS planes > follow the > + * Y and UV planes i.e., planes 0 and 1 are used for Y and UV > surfaces, > + * planes 2 and 3 for the respective CCS. > + */ > +#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, > 7) > + > /* > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized > macroblocks > *
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 5ba481f49931..8bc0b31597d8 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -421,6 +421,19 @@ extern "C" { */ #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) +/* + * Intel color control surfaces (CCS) for Gen-12 media compression + * + * The main surface is Y-tiled and at plane index 0, the CCS is linear and + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in + * main surface. In other words, 4 bits in CCS map to a main surface cache + * line pair. The main surface pitch is required to be a multiple of four + * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the + * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, + * planes 2 and 3 for the respective CCS. + */ +#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) + /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks *