diff mbox series

[11/17] drm/i915: s/init_cdclk/init_cdclk_hw/

Message ID 20200120174728.21095-12-ville.syrjala@linux.intel.com
State New, archived
Headers show
Series drm/i915: Global state rework | expand

Commit Message

Ville Syrjälä Jan. 20, 2020, 5:47 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Give the cdclk init/uninit functions a _hw suffix to make
it clear they are about initializing the actual hardware.
I'll be wanting to to add a intel_cdclk_init() which is
purely initializing software structures.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 24 +++++++++----------
 drivers/gpu/drm/i915/display/intel_cdclk.h    |  4 ++--
 .../drm/i915/display/intel_display_power.c    | 16 ++++++-------
 3 files changed, 22 insertions(+), 22 deletions(-)

Comments

Imre Deak Jan. 24, 2020, 3:08 p.m. UTC | #1
On Mon, Jan 20, 2020 at 07:47:21PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Give the cdclk init/uninit functions a _hw suffix to make
> it clear they are about initializing the actual hardware.
> I'll be wanting to to add a intel_cdclk_init() which is
> purely initializing software structures.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c    | 24 +++++++++----------
>  drivers/gpu/drm/i915/display/intel_cdclk.h    |  4 ++--
>  .../drm/i915/display/intel_display_power.c    | 16 ++++++-------
>  3 files changed, 22 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 002044e80868..701a63c3ca38 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1122,7 +1122,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  	dev_priv->cdclk.hw.vco = -1;
>  }
>  
> -static void skl_init_cdclk(struct drm_i915_private *dev_priv)
> +static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_cdclk_config cdclk_config;
>  
> @@ -1151,7 +1151,7 @@ static void skl_init_cdclk(struct drm_i915_private *dev_priv)
>  	skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
>  }
>  
> -static void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
> +static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
>  
> @@ -1681,7 +1681,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  	dev_priv->cdclk.hw.vco = -1;
>  }
>  
> -static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
> +static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_cdclk_config cdclk_config;
>  
> @@ -1706,7 +1706,7 @@ static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
>  	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
>  }
>  
> -static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> +static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
>  
> @@ -1719,7 +1719,7 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
>  }
>  
>  /**
> - * intel_cdclk_init - Initialize CDCLK
> + * intel_cdclk_init_hw - Initialize CDCLK hardware
>   * @i915: i915 device
>   *
>   * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
> @@ -1727,27 +1727,27 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
>   * during the display core initialization sequence, after which the DMC will
>   * take care of turning CDCLK off/on as needed.
>   */
> -void intel_cdclk_init(struct drm_i915_private *i915)
> +void intel_cdclk_init_hw(struct drm_i915_private *i915)
>  {
>  	if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
> -		bxt_init_cdclk(i915);
> +		bxt_cdclk_init_hw(i915);
>  	else if (IS_GEN9_BC(i915))
> -		skl_init_cdclk(i915);
> +		skl_cdclk_init_hw(i915);
>  }
>  
>  /**
> - * intel_cdclk_uninit - Uninitialize CDCLK
> + * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
>   * @i915: i915 device
>   *
>   * Uninitialize CDCLK. This is done only during the display core
>   * uninitialization sequence.
>   */
> -void intel_cdclk_uninit(struct drm_i915_private *i915)
> +void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
>  {
>  	if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915))
> -		bxt_uninit_cdclk(i915);
> +		bxt_cdclk_uninit_hw(i915);
>  	else if (IS_GEN9_BC(i915))
> -		skl_uninit_cdclk(i915);
> +		skl_cdclk_uninit_hw(i915);
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index a3fb7b8e8d31..4b965db07720 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -23,8 +23,8 @@ struct intel_cdclk_vals {
>  };
>  
>  int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
> -void intel_cdclk_init(struct drm_i915_private *i915);
> -void intel_cdclk_uninit(struct drm_i915_private *i915);
> +void intel_cdclk_init_hw(struct drm_i915_private *i915);
> +void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
>  void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
>  void intel_update_cdclk(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 2dc00d4b115b..3412c56bea6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4763,7 +4763,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>  
>  	mutex_unlock(&power_domains->lock);
>  
> -	intel_cdclk_init(dev_priv);
> +	intel_cdclk_init_hw(dev_priv);
>  
>  	gen9_dbuf_enable(dev_priv);
>  
> @@ -4780,7 +4780,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
>  
>  	gen9_dbuf_disable(dev_priv);
>  
> -	intel_cdclk_uninit(dev_priv);
> +	intel_cdclk_uninit_hw(dev_priv);
>  
>  	/* The spec doesn't call for removing the reset handshake flag */
>  	/* disable PG1 and Misc I/O */
> @@ -4824,7 +4824,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
>  
>  	mutex_unlock(&power_domains->lock);
>  
> -	intel_cdclk_init(dev_priv);
> +	intel_cdclk_init_hw(dev_priv);
>  
>  	gen9_dbuf_enable(dev_priv);
>  
> @@ -4841,7 +4841,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
>  
>  	gen9_dbuf_disable(dev_priv);
>  
> -	intel_cdclk_uninit(dev_priv);
> +	intel_cdclk_uninit_hw(dev_priv);
>  
>  	/* The spec doesn't call for removing the reset handshake flag */
>  
> @@ -4883,7 +4883,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
>  	mutex_unlock(&power_domains->lock);
>  
>  	/* 5. Enable CD clock */
> -	intel_cdclk_init(dev_priv);
> +	intel_cdclk_init_hw(dev_priv);
>  
>  	/* 6. Enable DBUF */
>  	gen9_dbuf_enable(dev_priv);
> @@ -4905,7 +4905,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
>  	gen9_dbuf_disable(dev_priv);
>  
>  	/* 3. Disable CD clock */
> -	intel_cdclk_uninit(dev_priv);
> +	intel_cdclk_uninit_hw(dev_priv);
>  
>  	/*
>  	 * 4. Disable Power Well 1 (PG1).
> @@ -4997,7 +4997,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
>  	mutex_unlock(&power_domains->lock);
>  
>  	/* 4. Enable CDCLK. */
> -	intel_cdclk_init(dev_priv);
> +	intel_cdclk_init_hw(dev_priv);
>  
>  	/* 5. Enable DBUF. */
>  	icl_dbuf_enable(dev_priv);
> @@ -5026,7 +5026,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
>  	icl_dbuf_disable(dev_priv);
>  
>  	/* 3. Disable CD clock */
> -	intel_cdclk_uninit(dev_priv);
> +	intel_cdclk_uninit_hw(dev_priv);
>  
>  	/*
>  	 * 4. Disable Power Well 1 (PG1).
> -- 
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 002044e80868..701a63c3ca38 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1122,7 +1122,7 @@  static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	dev_priv->cdclk.hw.vco = -1;
 }
 
-static void skl_init_cdclk(struct drm_i915_private *dev_priv)
+static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_config cdclk_config;
 
@@ -1151,7 +1151,7 @@  static void skl_init_cdclk(struct drm_i915_private *dev_priv)
 	skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
 }
 
-static void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
+static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
 
@@ -1681,7 +1681,7 @@  static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	dev_priv->cdclk.hw.vco = -1;
 }
 
-static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
+static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_config cdclk_config;
 
@@ -1706,7 +1706,7 @@  static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
 	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
 }
 
-static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
+static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
 
@@ -1719,7 +1719,7 @@  static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
 }
 
 /**
- * intel_cdclk_init - Initialize CDCLK
+ * intel_cdclk_init_hw - Initialize CDCLK hardware
  * @i915: i915 device
  *
  * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
@@ -1727,27 +1727,27 @@  static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
  * during the display core initialization sequence, after which the DMC will
  * take care of turning CDCLK off/on as needed.
  */
-void intel_cdclk_init(struct drm_i915_private *i915)
+void intel_cdclk_init_hw(struct drm_i915_private *i915)
 {
 	if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
-		bxt_init_cdclk(i915);
+		bxt_cdclk_init_hw(i915);
 	else if (IS_GEN9_BC(i915))
-		skl_init_cdclk(i915);
+		skl_cdclk_init_hw(i915);
 }
 
 /**
- * intel_cdclk_uninit - Uninitialize CDCLK
+ * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
  * @i915: i915 device
  *
  * Uninitialize CDCLK. This is done only during the display core
  * uninitialization sequence.
  */
-void intel_cdclk_uninit(struct drm_i915_private *i915)
+void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
 {
 	if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915))
-		bxt_uninit_cdclk(i915);
+		bxt_cdclk_uninit_hw(i915);
 	else if (IS_GEN9_BC(i915))
-		skl_uninit_cdclk(i915);
+		skl_cdclk_uninit_hw(i915);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index a3fb7b8e8d31..4b965db07720 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -23,8 +23,8 @@  struct intel_cdclk_vals {
 };
 
 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
-void intel_cdclk_init(struct drm_i915_private *i915);
-void intel_cdclk_uninit(struct drm_i915_private *i915);
+void intel_cdclk_init_hw(struct drm_i915_private *i915);
+void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
 void intel_update_cdclk(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2dc00d4b115b..3412c56bea6d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4763,7 +4763,7 @@  static void skl_display_core_init(struct drm_i915_private *dev_priv,
 
 	mutex_unlock(&power_domains->lock);
 
-	intel_cdclk_init(dev_priv);
+	intel_cdclk_init_hw(dev_priv);
 
 	gen9_dbuf_enable(dev_priv);
 
@@ -4780,7 +4780,7 @@  static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
 
 	gen9_dbuf_disable(dev_priv);
 
-	intel_cdclk_uninit(dev_priv);
+	intel_cdclk_uninit_hw(dev_priv);
 
 	/* The spec doesn't call for removing the reset handshake flag */
 	/* disable PG1 and Misc I/O */
@@ -4824,7 +4824,7 @@  static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
 
 	mutex_unlock(&power_domains->lock);
 
-	intel_cdclk_init(dev_priv);
+	intel_cdclk_init_hw(dev_priv);
 
 	gen9_dbuf_enable(dev_priv);
 
@@ -4841,7 +4841,7 @@  static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
 
 	gen9_dbuf_disable(dev_priv);
 
-	intel_cdclk_uninit(dev_priv);
+	intel_cdclk_uninit_hw(dev_priv);
 
 	/* The spec doesn't call for removing the reset handshake flag */
 
@@ -4883,7 +4883,7 @@  static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
 	mutex_unlock(&power_domains->lock);
 
 	/* 5. Enable CD clock */
-	intel_cdclk_init(dev_priv);
+	intel_cdclk_init_hw(dev_priv);
 
 	/* 6. Enable DBUF */
 	gen9_dbuf_enable(dev_priv);
@@ -4905,7 +4905,7 @@  static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
 	gen9_dbuf_disable(dev_priv);
 
 	/* 3. Disable CD clock */
-	intel_cdclk_uninit(dev_priv);
+	intel_cdclk_uninit_hw(dev_priv);
 
 	/*
 	 * 4. Disable Power Well 1 (PG1).
@@ -4997,7 +4997,7 @@  static void icl_display_core_init(struct drm_i915_private *dev_priv,
 	mutex_unlock(&power_domains->lock);
 
 	/* 4. Enable CDCLK. */
-	intel_cdclk_init(dev_priv);
+	intel_cdclk_init_hw(dev_priv);
 
 	/* 5. Enable DBUF. */
 	icl_dbuf_enable(dev_priv);
@@ -5026,7 +5026,7 @@  static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
 	icl_dbuf_disable(dev_priv);
 
 	/* 3. Disable CD clock */
-	intel_cdclk_uninit(dev_priv);
+	intel_cdclk_uninit_hw(dev_priv);
 
 	/*
 	 * 4. Disable Power Well 1 (PG1).