From patchwork Mon Jan 20 17:47:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11342693 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 07E81921 for ; Mon, 20 Jan 2020 17:47:58 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E3A6822527 for ; Mon, 20 Jan 2020 17:47:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E3A6822527 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 640706EAA8; Mon, 20 Jan 2020 17:47:57 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4A5D46EA55 for ; Mon, 20 Jan 2020 17:47:55 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Jan 2020 09:47:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,342,1574150400"; d="scan'208";a="306978212" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga001.jf.intel.com with SMTP; 20 Jan 2020 09:47:52 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 20 Jan 2020 19:47:52 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Jan 2020 19:47:18 +0200 Message-Id: <20200120174728.21095-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200120174728.21095-1-ville.syrjala@linux.intel.com> References: <20200120174728.21095-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 08/17] drm/i915: Simplify intel_set_cdclk_{pre, post}_plane_update() calling convention X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Move all the old vs. new state shenanigans into intel_set_cdclk_{pre,post}_plane_update() so that the caller doesn't need to know any of it. Signed-off-by: Ville Syrjälä Reviewed-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 44 ++++++++++---------- drivers/gpu/drm/i915/display/intel_cdclk.h | 12 +----- drivers/gpu/drm/i915/display/intel_display.c | 10 +---- 3 files changed, 26 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 2a5491eb8af3..a2b1401dcfbb 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1887,41 +1887,41 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, } /** - * intel_set_cdclk_pre_plane_update - Push the CDCLK configuration to the hardware - * @dev_priv: i915 device - * @old_state: old CDCLK configuration - * @new_state: new CDCLK configuration - * @pipe: pipe with which to synchronize the update + * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware + * @state: intel atomic state * - * Program the hardware before updating the HW plane state based on the passed - * in CDCLK configuration, if necessary. + * Program the hardware before updating the HW plane state based on the + * new CDCLK state, if necessary. */ void -intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *old_state, - const struct intel_cdclk_config *new_state, - enum pipe pipe) +intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) { + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + /* called after intel_cdclk_swap_state()! */ + const struct intel_cdclk_config *old_state = &state->cdclk.actual; + const struct intel_cdclk_config *new_state = &dev_priv->cdclk.actual; + enum pipe pipe = state->cdclk.pipe; + if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk) intel_set_cdclk(dev_priv, new_state, pipe); } /** - * intel_set_cdclk_post_plane_update - Push the CDCLK configuration to the hardware - * @dev_priv: i915 device - * @old_state: old CDCLK configuration - * @new_state: new CDCLK configuration - * @pipe: pipe with which to synchronize the update + * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware + * @state: intel atomic state * - * Program the hardware after updating the HW plane state based on the passed - * in CDCLK configuration, if necessary. + * Program the hardware before updating the HW plane state based on the + * new CDCLK state, if necessary. */ void -intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *old_state, - const struct intel_cdclk_config *new_state, - enum pipe pipe) +intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) { + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + /* called after intel_cdclk_swap_state()! */ + const struct intel_cdclk_config *old_state = &state->cdclk.actual; + const struct intel_cdclk_config *new_state = &dev_priv->cdclk.actual; + enum pipe pipe = state->cdclk.pipe; + if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk) intel_set_cdclk(dev_priv, new_state, pipe); } diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index 712cdaea4fef..a3fb7b8e8d31 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -33,16 +33,8 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b); void intel_cdclk_clear_state(struct intel_atomic_state *state); void intel_cdclk_swap_state(struct intel_atomic_state *state); -void -intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *old_state, - const struct intel_cdclk_config *new_state, - enum pipe pipe); -void -intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *old_state, - const struct intel_cdclk_config *new_state, - enum pipe pipe); +void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state); +void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state); void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config, const char *context); int intel_modeset_calc_cdclk(struct intel_atomic_state *state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index de2ab44b9150..25b0eab019cb 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15411,10 +15411,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) if (state->modeset) { drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); - intel_set_cdclk_pre_plane_update(dev_priv, - &state->cdclk.actual, - &dev_priv->cdclk.actual, - state->cdclk.pipe); + intel_set_cdclk_pre_plane_update(state); /* * SKL workaround: bspec recommends we disable the SAGV when we @@ -15450,10 +15447,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) if (state->modeset) { intel_encoders_update_complete(state); - intel_set_cdclk_post_plane_update(dev_priv, - &state->cdclk.actual, - &dev_priv->cdclk.actual, - state->cdclk.pipe); + intel_set_cdclk_post_plane_update(state); } /* FIXME: We should call drm_atomic_helper_commit_hw_done() here