From patchwork Sun Feb 2 23:06:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Lisovskiy, Stanislav" X-Patchwork-Id: 11361923 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 94387139A for ; Sun, 2 Feb 2020 23:10:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7C61F20643 for ; Sun, 2 Feb 2020 23:10:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7C61F20643 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B7086E14C; Sun, 2 Feb 2020 23:10:05 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4152A6E14C for ; Sun, 2 Feb 2020 23:10:04 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Feb 2020 15:10:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,395,1574150400"; d="scan'208";a="234397182" Received: from slisovsk-lenovo-ideapad-720s-13ikb.fi.intel.com ([10.237.72.89]) by orsmga006.jf.intel.com with ESMTP; 02 Feb 2020 15:10:02 -0800 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Date: Mon, 3 Feb 2020 01:06:28 +0200 Message-Id: <20200202230630.8975-5-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.24.1.485.gad05a3d8e5 In-Reply-To: <20200202230630.8975-1-stanislav.lisovskiy@intel.com> References: <20200202230630.8975-1-stanislav.lisovskiy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v17 4/6] drm/i915: Introduce parameterized DBUF_CTL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Now start using parameterized DBUF_CTL instead of hardcoded, this would allow shorter access functions when reading or storing entire state. Tried to implement it in a MMIO_PIPE manner, however DBUF_CTL1 address is higher than DBUF_CTL2, which implies that we have to now subtract from base rather than add. v2: - Removed unneeded DBUF_CTL_DIST and DBUF_CTL_ADDR macros. Started to use _PICK construct as suggested by Matt Roper. v3: - _DBUF_CTL_S* to DBUF_CTL_S*, changed X to "slice" in macro(Ville Syrjälä) - Introduced enum for enumerating DBUF slices(Ville Syrjälä) Reviewed-by: Ville Syrjälä Reviewed-by: Matt Roper Signed-off-by: Stanislav Lisovskiy --- .../drm/i915/display/intel_display_power.c | 40 ++++++++++--------- .../drm/i915/display/intel_display_power.h | 5 +++ drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 6 +-- drivers/gpu/drm/i915/intel_pm.c | 2 +- 5 files changed, 31 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 86e349bbc0af..9f978c977dcb 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1041,7 +1041,7 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) { - u32 tmp = intel_de_read(dev_priv, DBUF_CTL); + u32 tmp = intel_de_read(dev_priv, DBUF_CTL_S(0)); WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) != (DBUF_POWER_STATE | DBUF_POWER_REQUEST), @@ -4418,12 +4418,12 @@ bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv, static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) { - intel_dbuf_slice_set(dev_priv, DBUF_CTL, true); + intel_dbuf_slice_set(dev_priv, DBUF_CTL_S(0), true); } static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) { - intel_dbuf_slice_set(dev_priv, DBUF_CTL, false); + intel_dbuf_slice_set(dev_priv, DBUF_CTL_S(0), false); } static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv) @@ -4449,9 +4449,11 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, return; if (req_slices > hw_enabled_slices) - ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true); + ret = intel_dbuf_slice_set(dev_priv, + DBUF_CTL_S(DBUF_S2), true); else - ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false); + ret = intel_dbuf_slice_set(dev_priv, + DBUF_CTL_S(DBUF_S2), false); if (ret) dev_priv->enabled_dbuf_slices_num = req_slices; @@ -4459,16 +4461,16 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, static void icl_dbuf_enable(struct drm_i915_private *dev_priv) { - intel_de_write(dev_priv, DBUF_CTL_S1, - intel_de_read(dev_priv, DBUF_CTL_S1) | DBUF_POWER_REQUEST); - intel_de_write(dev_priv, DBUF_CTL_S2, - intel_de_read(dev_priv, DBUF_CTL_S2) | DBUF_POWER_REQUEST); - intel_de_posting_read(dev_priv, DBUF_CTL_S2); + intel_de_write(dev_priv, DBUF_CTL_S(0), + intel_de_read(dev_priv, DBUF_CTL_S(0)) | DBUF_POWER_REQUEST); + intel_de_write(dev_priv, DBUF_CTL_S(1), + intel_de_read(dev_priv, DBUF_CTL_S(1)) | DBUF_POWER_REQUEST); + intel_de_posting_read(dev_priv, DBUF_CTL_S(1)); udelay(10); - if (!(intel_de_read(dev_priv, DBUF_CTL_S1) & DBUF_POWER_STATE) || - !(intel_de_read(dev_priv, DBUF_CTL_S2) & DBUF_POWER_STATE)) + if (!(intel_de_read(dev_priv, DBUF_CTL_S(0)) & DBUF_POWER_STATE) || + !(intel_de_read(dev_priv, DBUF_CTL_S(1)) & DBUF_POWER_STATE)) drm_err(&dev_priv->drm, "DBuf power enable timeout\n"); else /* @@ -4480,16 +4482,16 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv) static void icl_dbuf_disable(struct drm_i915_private *dev_priv) { - intel_de_write(dev_priv, DBUF_CTL_S1, - intel_de_read(dev_priv, DBUF_CTL_S1) & ~DBUF_POWER_REQUEST); - intel_de_write(dev_priv, DBUF_CTL_S2, - intel_de_read(dev_priv, DBUF_CTL_S2) & ~DBUF_POWER_REQUEST); - intel_de_posting_read(dev_priv, DBUF_CTL_S2); + intel_de_write(dev_priv, DBUF_CTL_S(0), + intel_de_read(dev_priv, DBUF_CTL_S(0)) & ~DBUF_POWER_REQUEST); + intel_de_write(dev_priv, DBUF_CTL_S(1), + intel_de_read(dev_priv, DBUF_CTL_S(1)) & ~DBUF_POWER_REQUEST); + intel_de_posting_read(dev_priv, DBUF_CTL_S(1)); udelay(10); - if ((intel_de_read(dev_priv, DBUF_CTL_S1) & DBUF_POWER_STATE) || - (intel_de_read(dev_priv, DBUF_CTL_S2) & DBUF_POWER_STATE)) + if ((intel_de_read(dev_priv, DBUF_CTL_S(0)) & DBUF_POWER_STATE) || + (intel_de_read(dev_priv, DBUF_CTL_S(1)) & DBUF_POWER_STATE)) drm_err(&dev_priv->drm, "DBuf power disable timeout!\n"); else /* diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 2608a65af7fa..601e000ffd0d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -307,6 +307,11 @@ intel_display_power_put_async(struct drm_i915_private *i915, } #endif +enum dbuf_slice { + DBUF_S1, + DBUF_S2, +}; + #define with_intel_display_power(i915, domain, wf) \ for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 18475dd377ed..ae6700dc9d73 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -2902,7 +2902,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS); MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write); - MMIO_DH(DBUF_CTL, D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); + MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS); MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0bd431f6a011..dc206723f25e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7753,9 +7753,9 @@ enum { #define DISP_ARB_CTL2 _MMIO(0x45004) #define DISP_DATA_PARTITION_5_6 (1 << 6) #define DISP_IPC_ENABLE (1 << 3) -#define DBUF_CTL _MMIO(0x45008) -#define DBUF_CTL_S1 _MMIO(0x45008) -#define DBUF_CTL_S2 _MMIO(0x44FE8) +#define _DBUF_CTL_S1 0x45008 +#define _DBUF_CTL_S2 0x44FE8 +#define DBUF_CTL_S(slice) _MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2)) #define DBUF_POWER_REQUEST (1 << 31) #define DBUF_POWER_STATE (1 << 30) #define GEN7_MSG_CTL _MMIO(0x45010) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 89aa188c8cf5..f9e00ca61302 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3613,7 +3613,7 @@ u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv) * only that 1 slice enabled until we have a proper way for on-demand * toggling of the second slice. */ - if (0 && I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE) + if (0 && I915_READ(DBUF_CTL_S(DBUF_S2)) & DBUF_POWER_STATE) enabled_dbuf_slices_num++; return enabled_dbuf_slices_num;