@@ -1229,7 +1229,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
break;
default:
- MISSING_CASE(port_sel);
+ i915_MISSING_CASE(dev_priv, port_sel);
break;
}
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
@@ -2051,12 +2051,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
case 16:
return 256;
default:
- MISSING_CASE(cpp);
+ i915_MISSING_CASE(dev_priv, cpp);
return cpp;
}
break;
default:
- MISSING_CASE(fb->modifier);
+ i915_MISSING_CASE(dev_priv, fb->modifier);
return cpp;
}
}
@@ -2194,7 +2194,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
default:
- MISSING_CASE(fb->modifier);
+ i915_MISSING_CASE(dev_priv, fb->modifier);
return 0;
}
}
@@ -3433,7 +3433,7 @@ initial_plane_vma(struct drm_i915_private *i915,
plane_config->tiling;
break;
default:
- MISSING_CASE(plane_config->tiling);
+ i915_MISSING_CASE(i915, plane_config->tiling);
goto err_obj;
}
@@ -4225,7 +4225,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
dspcntr |= DISPPLANE_RGBX161616;
break;
default:
- MISSING_CASE(fb->format->format);
+ i915_MISSING_CASE(dev_priv, fb->format->format);
return 0;
}
@@ -7307,7 +7307,7 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
case AUX_CH_G:
return POWER_DOMAIN_AUX_G_TBT;
default:
- MISSING_CASE(dig_port->aux_ch);
+ i915_MISSING_CASE(dev_priv, dig_port->aux_ch);
return POWER_DOMAIN_AUX_C_TBT;
}
}
@@ -7328,7 +7328,7 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
case AUX_CH_G:
return POWER_DOMAIN_AUX_G;
default:
- MISSING_CASE(dig_port->aux_ch);
+ i915_MISSING_CASE(dev_priv, dig_port->aux_ch);
return POWER_DOMAIN_AUX_A;
}
}
@@ -10109,7 +10109,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
val |= PIPEMISC_DITHER_12_BPC;
break;
default:
- MISSING_CASE(crtc_state->pipe_bpp);
+ i915_MISSING_CASE(dev_priv, crtc_state->pipe_bpp);
break;
}
@@ -10149,7 +10149,7 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
case PIPEMISC_DITHER_12_BPC:
return 36;
default:
- MISSING_CASE(tmp);
+ i915_MISSING_CASE(dev_priv, tmp);
return 0;
}
}
@@ -10519,7 +10519,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
fb->modifier = I915_FORMAT_MOD_Yf_TILED;
break;
default:
- MISSING_CASE(tiling);
+ i915_MISSING_CASE(dev_priv, tiling);
goto error;
}
@@ -10861,7 +10861,7 @@ static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
id = DPLL_ID_LCPLL_2700;
break;
default:
- MISSING_CASE(ddi_pll_sel);
+ i915_MISSING_CASE(dev_priv, ddi_pll_sel);
/* fall through */
case PORT_CLK_SEL_NONE:
return;
@@ -11622,7 +11622,8 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
cntl |= MCURSOR_MODE_256_ARGB_AX;
break;
default:
- MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
+ i915_MISSING_CASE(dev_priv,
+ drm_rect_width(&plane_state->uapi.dst));
return 0;
}
@@ -12601,7 +12602,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
else if (linked->id == PLANE_SPRITE4)
plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
else
- MISSING_CASE(linked->id);
+ i915_MISSING_CASE(dev_priv, linked->id);
}
}
i915_MISSING_CASE macro includes the device information in the backtrace, so we know what device the warnings originate from. Covert MISSING_CASE calls with i915 specific i915_MISSING_CASE variant in functions where drm_i915_private struct pointer is readily available. The conversion was done automatically with below coccinelle semantic patch. @rule1@ identifier func, T; @@ func(...) { ... struct drm_i915_private *T = ...; <... -MISSING_CASE( +i915_MISSING_CASE(T, ...) ...> } @rule2@ identifier func, T; @@ func(struct drm_i915_private *T,...) { <... -MISSING_CASE( +i915_MISSING_CASE(T, ...) ...> } Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 29 ++++++++++---------- 1 file changed, 15 insertions(+), 14 deletions(-)