From patchwork Tue Feb 25 17:11:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11404271 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 541E4930 for ; Tue, 25 Feb 2020 17:11:39 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3C96D20CC7 for ; Tue, 25 Feb 2020 17:11:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3C96D20CC7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C4CDD6EB48; Tue, 25 Feb 2020 17:11:38 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 733536EB48 for ; Tue, 25 Feb 2020 17:11:37 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Feb 2020 09:11:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,484,1574150400"; d="scan'208";a="284724856" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by FMSMGA003.fm.intel.com with SMTP; 25 Feb 2020 09:11:35 -0800 Received: by stinkbox (sSMTP sendmail emulation); Tue, 25 Feb 2020 19:11:34 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 25 Feb 2020 19:11:08 +0200 Message-Id: <20200225171125.28885-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200225171125.28885-1-ville.syrjala@linux.intel.com> References: <20200225171125.28885-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 03/20] drm/i915: Add missing commas to dbuf tables X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The preferred style is to sprinkle commas after each array and structure initialization, whether or not it happens to be the last element/member (only exception being sentinel entries which never have anything after them). This leads to much prettier diffs if/when new elements/members get added to the end of the initialization. We're not bound by some ancient silly mandate to omit the final comma. Cc: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/intel_pm.c | 88 ++++++++++++++++----------------- 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 59fc461bc454..abeb4b19071f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4184,49 +4184,49 @@ static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] = { .active_pipes = BIT(PIPE_A), .dbuf_mask = { - [PIPE_A] = BIT(DBUF_S1) - } + [PIPE_A] = BIT(DBUF_S1), + }, }, { .active_pipes = BIT(PIPE_B), .dbuf_mask = { - [PIPE_B] = BIT(DBUF_S1) - } + [PIPE_B] = BIT(DBUF_S1), + }, }, { .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), .dbuf_mask = { [PIPE_A] = BIT(DBUF_S1), - [PIPE_B] = BIT(DBUF_S2) - } + [PIPE_B] = BIT(DBUF_S2), + }, }, { .active_pipes = BIT(PIPE_C), .dbuf_mask = { - [PIPE_C] = BIT(DBUF_S2) - } + [PIPE_C] = BIT(DBUF_S2), + }, }, { .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), .dbuf_mask = { [PIPE_A] = BIT(DBUF_S1), - [PIPE_C] = BIT(DBUF_S2) - } + [PIPE_C] = BIT(DBUF_S2), + }, }, { .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), .dbuf_mask = { [PIPE_B] = BIT(DBUF_S1), - [PIPE_C] = BIT(DBUF_S2) - } + [PIPE_C] = BIT(DBUF_S2), + }, }, { .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), .dbuf_mask = { [PIPE_A] = BIT(DBUF_S1), [PIPE_B] = BIT(DBUF_S1), - [PIPE_C] = BIT(DBUF_S2) - } + [PIPE_C] = BIT(DBUF_S2), + }, }, }; @@ -4246,100 +4246,100 @@ static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = { .active_pipes = BIT(PIPE_A), .dbuf_mask = { - [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2) - } + [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), + }, }, { .active_pipes = BIT(PIPE_B), .dbuf_mask = { - [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2) - } + [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), + }, }, { .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), .dbuf_mask = { [PIPE_A] = BIT(DBUF_S2), - [PIPE_B] = BIT(DBUF_S1) - } + [PIPE_B] = BIT(DBUF_S1), + }, }, { .active_pipes = BIT(PIPE_C), .dbuf_mask = { - [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1) - } + [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1), + }, }, { .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), .dbuf_mask = { [PIPE_A] = BIT(DBUF_S1), - [PIPE_C] = BIT(DBUF_S2) - } + [PIPE_C] = BIT(DBUF_S2), + }, }, { .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), .dbuf_mask = { [PIPE_B] = BIT(DBUF_S1), - [PIPE_C] = BIT(DBUF_S2) - } + [PIPE_C] = BIT(DBUF_S2), + }, }, { .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), .dbuf_mask = { [PIPE_A] = BIT(DBUF_S1), [PIPE_B] = BIT(DBUF_S1), - [PIPE_C] = BIT(DBUF_S2) - } + [PIPE_C] = BIT(DBUF_S2), + }, }, { .active_pipes = BIT(PIPE_D), .dbuf_mask = { - [PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1) - } + [PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1), + }, }, { .active_pipes = BIT(PIPE_A) | BIT(PIPE_D), .dbuf_mask = { [PIPE_A] = BIT(DBUF_S1), - [PIPE_D] = BIT(DBUF_S2) - } + [PIPE_D] = BIT(DBUF_S2), + }, }, { .active_pipes = BIT(PIPE_B) | BIT(PIPE_D), .dbuf_mask = { [PIPE_B] = BIT(DBUF_S1), - [PIPE_D] = BIT(DBUF_S2) - } + [PIPE_D] = BIT(DBUF_S2), + }, }, { .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D), .dbuf_mask = { [PIPE_A] = BIT(DBUF_S1), [PIPE_B] = BIT(DBUF_S1), - [PIPE_D] = BIT(DBUF_S2) - } + [PIPE_D] = BIT(DBUF_S2), + }, }, { .active_pipes = BIT(PIPE_C) | BIT(PIPE_D), .dbuf_mask = { [PIPE_C] = BIT(DBUF_S1), - [PIPE_D] = BIT(DBUF_S2) - } + [PIPE_D] = BIT(DBUF_S2), + }, }, { .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D), .dbuf_mask = { [PIPE_A] = BIT(DBUF_S1), [PIPE_C] = BIT(DBUF_S2), - [PIPE_D] = BIT(DBUF_S2) - } + [PIPE_D] = BIT(DBUF_S2), + }, }, { .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), .dbuf_mask = { [PIPE_B] = BIT(DBUF_S1), [PIPE_C] = BIT(DBUF_S2), - [PIPE_D] = BIT(DBUF_S2) - } + [PIPE_D] = BIT(DBUF_S2), + }, }, { .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), @@ -4347,8 +4347,8 @@ static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = [PIPE_A] = BIT(DBUF_S1), [PIPE_B] = BIT(DBUF_S1), [PIPE_C] = BIT(DBUF_S2), - [PIPE_D] = BIT(DBUF_S2) - } + [PIPE_D] = BIT(DBUF_S2), + }, }, };