From patchwork Wed Mar 18 23:59:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11446313 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2F31F159A for ; Wed, 18 Mar 2020 23:58:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1808B2076C for ; Wed, 18 Mar 2020 23:58:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1808B2076C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A90A06E23B; Wed, 18 Mar 2020 23:58:55 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0E78A6E23B for ; Wed, 18 Mar 2020 23:58:50 +0000 (UTC) IronPort-SDR: afdMiZwk3sACPqmemlRLVB0JG4qVCtsZygEqz4650uXcQv14lc5y6ulPD0Td6WXPfjGPxVLBXW owc+AtkE3Mbw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2020 16:58:49 -0700 IronPort-SDR: jyL+Uz3LX55Zj9t8mEvQmNRN7yKgB8Crfs+vEuufa5OV0892Aeqc6m15SviroX93TQnxCeQSxg ou17m04Ul2Ww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,569,1574150400"; d="scan'208";a="324346279" Received: from josouza-mobl2.jf.intel.com (HELO josouza-MOBL2.intel.com) ([10.24.15.8]) by orsmga001.jf.intel.com with ESMTP; 18 Mar 2020 16:58:48 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Wed, 18 Mar 2020 16:59:53 -0700 Message-Id: <20200318235956.118409-3-jose.souza@intel.com> X-Mailer: git-send-email 2.25.2 In-Reply-To: <20200318235956.118409-1-jose.souza@intel.com> References: <20200318235956.118409-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/6] drm/i915/display: Implement intel_display_power_wait_enable_ack() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Cooper Chiou , Kai-Heng Feng Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This function is meant to be used after intel_display_power_get_without_ack() this way we can be sure that the HW tied to the powerdomain will be powered and ready. Cc: Imre Deak Cc: Cooper Chiou Cc: Kai-Heng Feng Signed-off-by: José Roberto de Souza --- .../drm/i915/display/intel_display_power.c | 29 +++++++++++++++++++ .../drm/i915/display/intel_display_power.h | 9 ++++++ 2 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 9035b220dfa0..a7e531b64e16 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -2328,6 +2328,35 @@ intel_display_power_flush_work_sync(struct drm_i915_private *i915) drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref); } +/** + * intel_display_power_wait_enable_ack - wait for enabled hardware ack + * @dev_priv: i915 device instance + * @domain: power domain to reference + * + * This function must be called after intel_display_power_get_without_ack() and + * only in power domains that implements it. + */ +void intel_display_power_wait_enable_ack(struct drm_i915_private *dev_priv, + enum intel_display_power_domain domain) +{ + struct i915_power_domains *power_domains = &dev_priv->power_domains; + struct i915_power_well *power_well; + + mutex_lock(&power_domains->lock); + + for_each_power_domain_well_reverse(dev_priv, power_well, + BIT_ULL(domain)) { + if (drm_WARN_ON(&dev_priv->drm, + !power_well->desc->ops->wait_enable_ack)) + break; + + power_well->desc->ops->wait_enable_ack(dev_priv, power_well); + break; + } + + mutex_unlock(&power_domains->lock); +} + #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) /** * intel_display_power_put - release a power domain reference diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 5db86cc862c3..108096177deb 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -148,6 +148,13 @@ struct i915_power_well_ops { /* Returns the hw enabled state. */ bool (*is_enabled)(struct drm_i915_private *dev_priv, struct i915_power_well *power_well); + + /* + * Waits for hardware enabling ack, this is meant to be used together + * with enable_without_ack() and also optional. + */ + void (*wait_enable_ack)(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well); }; struct i915_power_well_regs { @@ -291,6 +298,8 @@ void __intel_display_power_put_async(struct drm_i915_private *i915, enum intel_display_power_domain domain, intel_wakeref_t wakeref); void intel_display_power_flush_work(struct drm_i915_private *i915); +void intel_display_power_wait_enable_ack(struct drm_i915_private *dev_priv, + enum intel_display_power_domain domain); #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) void intel_display_power_put(struct drm_i915_private *dev_priv, enum intel_display_power_domain domain,