From patchwork Thu Mar 19 16:38:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11447689 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9079592A for ; Thu, 19 Mar 2020 16:38:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 78AD42072C for ; Thu, 19 Mar 2020 16:38:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 78AD42072C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 62E6289DBD; Thu, 19 Mar 2020 16:38:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6D9D689DBD for ; Thu, 19 Mar 2020 16:38:51 +0000 (UTC) IronPort-SDR: Gg7PClKr8VezIFJ9mmphkTL29L6UsGTeP6pKCMijDdqT7mlOcEyuYiVSGd445v9OpWR6svNVyz biQCLm/tde9Q== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2020 09:38:50 -0700 IronPort-SDR: Vm0JmMnocVKKQyVh/3QgRGDFuehYJrHu65LKdwMHhtkYnbwkyuQ6gV84oOQZ3vgnzLWo/4jvYW ZyAVAQBv71sQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,572,1574150400"; d="scan'208";a="248592377" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga006.jf.intel.com with SMTP; 19 Mar 2020 09:38:48 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 19 Mar 2020 18:38:48 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 19 Mar 2020 18:38:43 +0200 Message-Id: <20200319163844.22783-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200319163844.22783-1-ville.syrjala@linux.intel.com> References: <20200319163844.22783-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/3] drm: Refactor intel_dp_compute_link_config_*() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Pull the common parts of intel_dp_compute_link_config_wide() and intel_dp_compute_link_config_fast() into a shared helper to avoid duplicated code. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 76 ++++++++++++++----------- 1 file changed, 44 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 85abcce492ca..8491ce8b8c15 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2014,34 +2014,47 @@ static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bp return bpp; } +static bool +intel_dp_link_config_valid(const struct intel_crtc_state *crtc_state, + int bpp, int link_clock, int lane_count) +{ + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + int output_bpp = intel_dp_output_bpp(crtc_state, bpp); + int mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, + output_bpp); + int link_avail = intel_dp_max_data_rate(link_clock, lane_count); + + return mode_rate <= link_avail; +} + /* Optimize link config in order: max bpp, min clock, min lanes */ static int intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config, + struct intel_crtc_state *crtc_state, const struct link_config_limits *limits) { - struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; - int bpp, clock, lane_count; - int mode_rate, link_clock, link_avail; + int bpp; for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { - int output_bpp = intel_dp_output_bpp(pipe_config, bpp); + int clock; - mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, - output_bpp); + for (clock = limits->min_clock; + clock <= limits->max_clock; + clock++) { + int lane_count; - for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { for (lane_count = limits->min_lane_count; lane_count <= limits->max_lane_count; lane_count <<= 1) { - link_clock = intel_dp->common_rates[clock]; - link_avail = intel_dp_max_data_rate(link_clock, - lane_count); + int link_clock = intel_dp->common_rates[clock]; - if (mode_rate <= link_avail) { - pipe_config->lane_count = lane_count; - pipe_config->pipe_bpp = bpp; - pipe_config->port_clock = link_clock; + if (intel_dp_link_config_valid(crtc_state, bpp, + link_clock, + lane_count)) { + crtc_state->pipe_bpp = bpp; + crtc_state->port_clock = link_clock; + crtc_state->lane_count = lane_count; return 0; } @@ -2055,31 +2068,30 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, /* Optimize link config in order: max bpp, min lanes, min clock */ static int intel_dp_compute_link_config_fast(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config, + struct intel_crtc_state *crtc_state, const struct link_config_limits *limits) { - const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; - int bpp, clock, lane_count; - int mode_rate, link_clock, link_avail; + int bpp; for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { - int output_bpp = intel_dp_output_bpp(pipe_config, bpp); - - mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, - output_bpp); + int lane_count; for (lane_count = limits->min_lane_count; lane_count <= limits->max_lane_count; lane_count <<= 1) { - for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { - link_clock = intel_dp->common_rates[clock]; - link_avail = intel_dp_max_data_rate(link_clock, - lane_count); - - if (mode_rate <= link_avail) { - pipe_config->lane_count = lane_count; - pipe_config->pipe_bpp = bpp; - pipe_config->port_clock = link_clock; + int clock; + + for (clock = limits->min_clock; + clock <= limits->max_clock; + clock++) { + int link_clock = intel_dp->common_rates[clock]; + + if (intel_dp_link_config_valid(crtc_state, bpp, + link_clock, + lane_count)) { + crtc_state->pipe_bpp = bpp; + crtc_state->port_clock = link_clock; + crtc_state->lane_count = lane_count; return 0; }