From patchwork Fri Mar 27 06:11:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vipin Anand X-Patchwork-Id: 11461705 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2422A15AB for ; Fri, 27 Mar 2020 06:12:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0C64420716 for ; Fri, 27 Mar 2020 06:12:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0C64420716 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E3ED6E985; Fri, 27 Mar 2020 06:12:51 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5A9C66E982 for ; Fri, 27 Mar 2020 06:12:37 +0000 (UTC) IronPort-SDR: 5NsH+00e7I6mdbpcrXC6VKIeYfCEn2u7vSE/IB2kLaR2OMFX1/TaW34jjhwd/q3TWUM+QBf6pt UicOhi6Os8cQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2020 23:12:37 -0700 IronPort-SDR: CHx5KwuCpQUU8K5T1FDuroSwsd4QsKT+K+VRBVdcx6eEiZ0XkRtg3iQMdp2vu+jnhxW3rwwXyI vjE9PBWkgq+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,311,1580803200"; d="scan'208";a="420987149" Received: from vipinana-nuc7i7bnh.iind.intel.com ([10.66.179.10]) by orsmga005.jf.intel.com with ESMTP; 26 Mar 2020 23:12:36 -0700 From: Vipin Anand To: intel-gfx@lists.freedesktop.org Date: Fri, 27 Mar 2020 11:41:09 +0530 Message-Id: <20200327061110.17371-7-vipin.anand@intel.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200327061110.17371-1-vipin.anand@intel.com> References: <20200327061110.17371-1-vipin.anand@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 6/7] drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Uma Shankar Blanking needs to be reduced to incorporate DP and HDMI timing/link bandwidth limitations for CEA modes (4k@60 at 10 bpp). DP can drive 17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will cause mode to blank out. Reduced Htotal by shortening the back porch and front porch within permissible limits. v2: This is marked as Not for merge and the responsibilty to program these custom timings will be on userspace. This patch is just for reference purposes. This is based on Ville's recommendation. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c7424e2a04a3..3ab1fadb2ea3 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -616,9 +616,11 @@ intel_dp_mode_valid(struct drm_connector *connector, { struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); struct intel_connector *intel_connector = to_intel_connector(connector); + struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector); struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; struct drm_i915_private *dev_priv = to_i915(connector->dev); int target_clock = mode->clock; + struct intel_lspcon *lspcon = enc_to_intel_lspcon(intel_encoder); int max_rate, mode_rate, max_lanes, max_link_clock; int max_dotclk; u16 dsc_max_output_bpp = 0; @@ -638,6 +640,20 @@ intel_dp_mode_valid(struct drm_connector *connector, target_clock = fixed_mode->clock; } + /* + * Reducing Blanking to incorporate DP and HDMI timing/link bandwidth + * limitations for CEA modes (4k@60 at 10 bpp). DP can drive 17.28Gbs + * while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will + * cause mode to blank out. Reduced Htotal by shortening the back porch + * and front porch within permissible limits. + */ + if (lspcon->active && lspcon->hdr_supported && + mode->clock > 570000) { + mode->clock = 570000; + mode->htotal -= 180; + mode->hsync_start -= 72; + mode->hsync_end -= 72; + } max_link_clock = intel_dp_max_link_rate(intel_dp); max_lanes = intel_dp_max_lane_count(intel_dp);