From patchwork Tue Apr 7 21:45:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 11479041 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D850E92C for ; Tue, 7 Apr 2020 22:04:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C0FC520747 for ; Tue, 7 Apr 2020 22:04:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C0FC520747 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=etezian.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 275936E914; Tue, 7 Apr 2020 22:04:38 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from 16.mo7.mail-out.ovh.net (16.mo7.mail-out.ovh.net [46.105.72.216]) by gabe.freedesktop.org (Postfix) with ESMTPS id 412FD6E914 for ; Tue, 7 Apr 2020 22:04:36 +0000 (UTC) Received: from player734.ha.ovh.net (unknown [10.108.35.210]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id D753B15D99F for ; Tue, 7 Apr 2020 23:45:35 +0200 (CEST) Received: from etezian.org (213-243-141-64.bb.dnainternet.fi [213.243.141.64]) (Authenticated sender: andi@etezian.org) by player734.ha.ovh.net (Postfix) with ESMTPSA id 1467911122846; Tue, 7 Apr 2020 21:45:30 +0000 (UTC) From: Andi Shyti To: Intel GFX Date: Wed, 8 Apr 2020 00:45:02 +0300 Message-Id: <20200407214502.217567-3-andi@etezian.org> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200407214502.217567-1-andi@etezian.org> References: <20200407214502.217567-1-andi@etezian.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17617800269751894621 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedrudeigddtudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgsehtkeertdertdejnecuhfhrohhmpeetnhguihcuufhhhihtihcuoegrnhguihesvghtvgiiihgrnhdrohhrgheqnecukfhppedtrddtrddtrddtpddvudefrddvgeefrddugedurdeigeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejfeegrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheprghnughisegvthgviihirghnrdhorhhgpdhrtghpthhtohepihhnthgvlhdqghhfgieslhhishhtshdrfhhrvggvuggvshhkthhophdrohhrgh Subject: [Intel-gfx] [PATCH v7 2/2] drm/i915/gt: move remaining debugfs interfaces into gt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Andi Shyti The following interfaces: i915_wedged i915_forcewake_user i915_gem_interrupt i915_rcs_topology i915_sseu_status are dependent on gt values. Put them inside gt/ and drop the "i915_" prefix name. This would be the new structure: dri/0/gt | +-- forcewake_user | +-- interrupt_info | \-- reset For backwards compatibility with existing igt (and the slight semantic difference between operating on the i915 abi entry points and the deep gt info): dri/0 | +-- i915_wedged | \-- i915_forcewake_user remain at the top level. Signed-off-by: Andi Shyti Reviewed-by: Tvrtko Ursulin Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/debugfs_gt.c | 48 ++++++- drivers/gpu/drm/i915/gt/debugfs_gt_irq.c | 162 +++++++++++++++++++++++ drivers/gpu/drm/i915/gt/debugfs_gt_irq.h | 15 +++ drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 32 +++++ drivers/gpu/drm/i915/i915_debugfs.c | 82 +----------- 6 files changed, 258 insertions(+), 82 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt_irq.c create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt_irq.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 2fce8b0040f3..6962c981dd54 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -79,6 +79,7 @@ gt-y += \ gt/debugfs_engines.o \ gt/debugfs_gt.o \ gt/debugfs_gt_pm.o \ + gt/debugfs_gt_irq.o \ gt/gen6_ppgtt.o \ gt/gen7_renderclear.o \ gt/gen8_ppgtt.o \ diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c b/drivers/gpu/drm/i915/gt/debugfs_gt.c index 1de5fbaa1cf9..91ae6d47141b 100644 --- a/drivers/gpu/drm/i915/gt/debugfs_gt.c +++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c @@ -8,9 +8,52 @@ #include "debugfs_engines.h" #include "debugfs_gt.h" +#include "debugfs_gt_irq.h" #include "debugfs_gt_pm.h" -#include "uc/intel_uc_debugfs.h" #include "i915_drv.h" +#include "intel_gt_pm.h" +#include "intel_gt_requests.h" +#include "uc/intel_uc_debugfs.h" + +static int reset_show(void *data, u64 *val) +{ + struct intel_gt *gt = data; + int ret = intel_gt_terminally_wedged(gt); + + switch (ret) { + case -EIO: + *val = 1; + return 0; + case 0: + *val = 0; + return 0; + default: + return ret; + } +} + +static int reset_store(void *data, u64 val) +{ + struct intel_gt *gt = data; + + /* Flush any previous reset before applying for a new one */ + wait_event(gt->reset.queue, + !test_bit(I915_RESET_BACKOFF, >->reset.flags)); + + intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE, + "Manually reset engine mask to %llx", val); + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(reset_fops, reset_show, reset_store, "%llu\n"); + +static void __debugfs_gt_register(struct intel_gt *gt, struct dentry *root) +{ + static const struct debugfs_gt_file files[] = { + { "reset", &reset_fops, NULL }, + }; + + intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt); +} void debugfs_gt_register(struct intel_gt *gt) { @@ -23,8 +66,11 @@ void debugfs_gt_register(struct intel_gt *gt) if (IS_ERR(root)) return; + __debugfs_gt_register(gt, root); + debugfs_engines_register(gt, root); debugfs_gt_pm_register(gt, root); + debugfs_gt_register_irq(gt, root); intel_uc_debugfs_register(>->uc, root); } diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_irq.c b/drivers/gpu/drm/i915/gt/debugfs_gt_irq.c new file mode 100644 index 000000000000..8aaf76dfc573 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_irq.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: MIT + +/* + * Copyright © 2020 Intel Corporation + */ + +#include "debugfs_gt.h" +#include "debugfs_gt_irq.h" +#include "i915_drv.h" + +static int interrupt_info_show(struct seq_file *m, void *data) +{ + struct intel_gt *gt = m->private; + struct drm_i915_private *i915 = gt->i915; + struct intel_uncore *uncore = gt->uncore; + struct intel_engine_cs *engine; + enum intel_engine_id id; + intel_wakeref_t wakeref; + int i; + + wakeref = intel_runtime_pm_get(uncore->rpm); + + if (IS_CHERRYVIEW(i915)) { + seq_printf(m, "Master Interrupt Control:\t%08x\n", + intel_uncore_read(uncore, GEN8_MASTER_IRQ)); + + for (i = 0; i < 4; i++) { + seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IMR(i))); + seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IIR(i))); + seq_printf(m, "GT Interrupt IER %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IER(i))); + } + + } else if (INTEL_GEN(i915) >= 11) { + seq_printf(m, "Master Interrupt Control: %08x\n", + intel_uncore_read(uncore, GEN11_GFX_MSTR_IRQ)); + + seq_printf(m, "Render/Copy Intr Enable: %08x\n", + intel_uncore_read(uncore, + GEN11_RENDER_COPY_INTR_ENABLE)); + seq_printf(m, "VCS/VECS Intr Enable: %08x\n", + intel_uncore_read(uncore, + GEN11_VCS_VECS_INTR_ENABLE)); + seq_printf(m, "GUC/SG Intr Enable:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUC_SG_INTR_ENABLE)); + seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n", + intel_uncore_read(uncore, + GEN11_GPM_WGBOXPERF_INTR_ENABLE)); + seq_printf(m, "Crypto Intr Enable:\t %08x\n", + intel_uncore_read(uncore, + GEN11_CRYPTO_RSVD_INTR_ENABLE)); + seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUNIT_CSME_INTR_ENABLE)); + + } else if (INTEL_GEN(i915) >= 8) { + seq_printf(m, "Master Interrupt Control:\t%08x\n", + intel_uncore_read(uncore, GEN8_MASTER_IRQ)); + + for (i = 0; i < 4; i++) { + seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IMR(i))); + seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IIR(i))); + seq_printf(m, "GT Interrupt IER %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IER(i))); + } + + } else if (IS_VALLEYVIEW(i915)) { + seq_printf(m, "Master IER:\t%08x\n", + intel_uncore_read(uncore, VLV_MASTER_IER)); + + seq_printf(m, "Render IER:\t%08x\n", + intel_uncore_read(uncore, GTIER)); + seq_printf(m, "Render IIR:\t%08x\n", + intel_uncore_read(uncore, GTIIR)); + seq_printf(m, "Render IMR:\t%08x\n", + intel_uncore_read(uncore, GTIMR)); + + seq_printf(m, "PM IER:\t\t%08x\n", + intel_uncore_read(uncore, GEN6_PMIER)); + seq_printf(m, "PM IIR:\t\t%08x\n", + intel_uncore_read(uncore, GEN6_PMIIR)); + seq_printf(m, "PM IMR:\t\t%08x\n", + intel_uncore_read(uncore, GEN6_PMIMR)); + + } else if (!HAS_PCH_SPLIT(i915)) { + seq_printf(m, "Interrupt enable: %08x\n", + intel_uncore_read(uncore, GEN2_IER)); + seq_printf(m, "Interrupt identity: %08x\n", + intel_uncore_read(uncore, GEN2_IIR)); + seq_printf(m, "Interrupt mask: %08x\n", + intel_uncore_read(uncore, GEN2_IMR)); + } else { + seq_printf(m, "Graphics Interrupt enable: %08x\n", + intel_uncore_read(uncore, GTIER)); + seq_printf(m, "Graphics Interrupt identity: %08x\n", + intel_uncore_read(uncore, GTIIR)); + seq_printf(m, "Graphics Interrupt mask: %08x\n", + intel_uncore_read(uncore, GTIMR)); + } + + if (INTEL_GEN(i915) >= 11) { + seq_printf(m, "RCS Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_RCS0_RSVD_INTR_MASK)); + seq_printf(m, "BCS Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_BCS_RSVD_INTR_MASK)); + seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_VCS0_VCS1_INTR_MASK)); + seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_VCS2_VCS3_INTR_MASK)); + seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_VECS0_VECS1_INTR_MASK)); + seq_printf(m, "GUC/SG Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUC_SG_INTR_MASK)); + seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n", + intel_uncore_read(uncore, + GEN11_GPM_WGBOXPERF_INTR_MASK)); + seq_printf(m, "Crypto Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_CRYPTO_RSVD_INTR_MASK)); + seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUNIT_CSME_INTR_MASK)); + + } else if (INTEL_GEN(i915) >= 6) { + for_each_engine(engine, gt, id) { + seq_printf(m, + "Graphics Interrupt mask (%s): %08x\n", + engine->name, ENGINE_READ(engine, RING_IMR)); + } + } + + intel_runtime_pm_put(uncore->rpm, wakeref); + + return 0; +} +DEFINE_GT_DEBUGFS_ATTRIBUTE(interrupt_info); + +void debugfs_gt_register_irq(struct intel_gt *gt, struct dentry *root) +{ + static const struct debugfs_gt_file files[] = { + { "interrupt_info", &interrupt_info_fops, NULL }, + }; + + intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt); +} diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_irq.h b/drivers/gpu/drm/i915/gt/debugfs_gt_irq.h new file mode 100644 index 000000000000..f3d601b3d019 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_irq.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ + +/* + * Copyright © 2020 Intel Corporation + */ + +#ifndef DEBUGFS_GT_IRQ_H +#define DEBUGFS_GT_IRQ_H + +struct intel_gt; +struct dentry; + +void debugfs_gt_register_irq(struct intel_gt *gt, struct dentry *root); + +#endif /* DEBUGFS_GT_IRQ_H */ diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c index aab30d908072..c94a946e0adb 100644 --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c @@ -10,6 +10,7 @@ #include "debugfs_gt_pm.h" #include "i915_drv.h" #include "intel_gt.h" +#include "intel_gt_pm.h" #include "intel_llc.h" #include "intel_rc6.h" #include "intel_rps.h" @@ -17,6 +18,36 @@ #include "intel_sideband.h" #include "intel_uncore.h" +static int forcewake_user_open(struct inode *inode, struct file *file) +{ + struct intel_gt *gt = inode->i_private; + + atomic_inc(>->user_wakeref); + intel_gt_pm_get(gt); + if (INTEL_GEN(gt->i915) >= 6) + intel_uncore_forcewake_user_get(gt->uncore); + + return 0; +} + +static int forcewake_user_release(struct inode *inode, struct file *file) +{ + struct intel_gt *gt = inode->i_private; + + if (INTEL_GEN(gt->i915) >= 6) + intel_uncore_forcewake_user_put(gt->uncore); + intel_gt_pm_put(gt); + atomic_dec(>->user_wakeref); + + return 0; +} + +static const struct file_operations forcewake_user_fops = { + .owner = THIS_MODULE, + .open = forcewake_user_open, + .release = forcewake_user_release, +}; + static int fw_domains_show(struct seq_file *m, void *data) { struct intel_gt *gt = m->private; @@ -597,6 +628,7 @@ void debugfs_gt_pm_register(struct intel_gt *gt, struct dentry *root) { "drpc", &drpc_fops, NULL }, { "frequency", &frequency_fops, NULL }, { "forcewake", &fw_domains_fops, NULL }, + { "forcewake_user", &forcewake_user_fops, NULL}, { "llc", &llc_fops, llc_eval }, { "rps_boost", &rps_boost_fops, rps_eval }, }; diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 4552b958f352..d05de62b4729 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -426,9 +426,8 @@ static void gen8_display_interrupt_info(struct seq_file *m) static int i915_interrupt_info(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); - struct intel_engine_cs *engine; intel_wakeref_t wakeref; - int i, pipe; + int pipe; wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); @@ -474,15 +473,6 @@ static int i915_interrupt_info(struct seq_file *m, void *data) I915_READ(DPINVGTT)); intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, pref); - for (i = 0; i < 4; i++) { - seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", - i, I915_READ(GEN8_GT_IMR(i))); - seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", - i, I915_READ(GEN8_GT_IIR(i))); - seq_printf(m, "GT Interrupt IER %d:\t%08x\n", - i, I915_READ(GEN8_GT_IER(i))); - } - seq_printf(m, "PCU interrupt mask:\t%08x\n", I915_READ(GEN8_PCU_IMR)); seq_printf(m, "PCU interrupt identity:\t%08x\n", @@ -493,19 +483,6 @@ static int i915_interrupt_info(struct seq_file *m, void *data) seq_printf(m, "Master Interrupt Control: %08x\n", I915_READ(GEN11_GFX_MSTR_IRQ)); - seq_printf(m, "Render/Copy Intr Enable: %08x\n", - I915_READ(GEN11_RENDER_COPY_INTR_ENABLE)); - seq_printf(m, "VCS/VECS Intr Enable: %08x\n", - I915_READ(GEN11_VCS_VECS_INTR_ENABLE)); - seq_printf(m, "GUC/SG Intr Enable:\t %08x\n", - I915_READ(GEN11_GUC_SG_INTR_ENABLE)); - seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n", - I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE)); - seq_printf(m, "Crypto Intr Enable:\t %08x\n", - I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE)); - seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n", - I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE)); - seq_printf(m, "Display Interrupt Control:\t%08x\n", I915_READ(GEN11_DISPLAY_INT_CTL)); @@ -514,15 +491,6 @@ static int i915_interrupt_info(struct seq_file *m, void *data) seq_printf(m, "Master Interrupt Control:\t%08x\n", I915_READ(GEN8_MASTER_IRQ)); - for (i = 0; i < 4; i++) { - seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", - i, I915_READ(GEN8_GT_IMR(i))); - seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", - i, I915_READ(GEN8_GT_IIR(i))); - seq_printf(m, "GT Interrupt IER %d:\t%08x\n", - i, I915_READ(GEN8_GT_IER(i))); - } - gen8_display_interrupt_info(m); } else if (IS_VALLEYVIEW(dev_priv)) { intel_wakeref_t pref; @@ -556,20 +524,6 @@ static int i915_interrupt_info(struct seq_file *m, void *data) seq_printf(m, "Master IER:\t%08x\n", I915_READ(VLV_MASTER_IER)); - seq_printf(m, "Render IER:\t%08x\n", - I915_READ(GTIER)); - seq_printf(m, "Render IIR:\t%08x\n", - I915_READ(GTIIR)); - seq_printf(m, "Render IMR:\t%08x\n", - I915_READ(GTIMR)); - - seq_printf(m, "PM IER:\t\t%08x\n", - I915_READ(GEN6_PMIER)); - seq_printf(m, "PM IIR:\t\t%08x\n", - I915_READ(GEN6_PMIIR)); - seq_printf(m, "PM IMR:\t\t%08x\n", - I915_READ(GEN6_PMIMR)); - pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); seq_printf(m, "Port hotplug:\t%08x\n", I915_READ(PORT_HOTPLUG_EN)); @@ -603,40 +557,6 @@ static int i915_interrupt_info(struct seq_file *m, void *data) I915_READ(SDEIIR)); seq_printf(m, "South Display Interrupt mask: %08x\n", I915_READ(SDEIMR)); - seq_printf(m, "Graphics Interrupt enable: %08x\n", - I915_READ(GTIER)); - seq_printf(m, "Graphics Interrupt identity: %08x\n", - I915_READ(GTIIR)); - seq_printf(m, "Graphics Interrupt mask: %08x\n", - I915_READ(GTIMR)); - } - - if (INTEL_GEN(dev_priv) >= 11) { - seq_printf(m, "RCS Intr Mask:\t %08x\n", - I915_READ(GEN11_RCS0_RSVD_INTR_MASK)); - seq_printf(m, "BCS Intr Mask:\t %08x\n", - I915_READ(GEN11_BCS_RSVD_INTR_MASK)); - seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n", - I915_READ(GEN11_VCS0_VCS1_INTR_MASK)); - seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n", - I915_READ(GEN11_VCS2_VCS3_INTR_MASK)); - seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n", - I915_READ(GEN11_VECS0_VECS1_INTR_MASK)); - seq_printf(m, "GUC/SG Intr Mask:\t %08x\n", - I915_READ(GEN11_GUC_SG_INTR_MASK)); - seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n", - I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK)); - seq_printf(m, "Crypto Intr Mask:\t %08x\n", - I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK)); - seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n", - I915_READ(GEN11_GUNIT_CSME_INTR_MASK)); - - } else if (INTEL_GEN(dev_priv) >= 6) { - for_each_uabi_engine(engine, dev_priv) { - seq_printf(m, - "Graphics Interrupt mask (%s): %08x\n", - engine->name, ENGINE_READ(engine, RING_IMR)); - } } intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);