| Message ID | 20200430154735.22434-6-mika.kuoppala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate" | expand |
Quoting Mika Kuoppala (2020-04-30 16:47:32) > Aim for completeness for invalidating everything > and mark state pointers stale. > > Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> There's a confusing mention that the indirect state pointers are not saved in the context... But we still need to invalidate if we rebind new buffers at the old pointer locations. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
Mika Kuoppala <mika.kuoppala@linux.intel.com> writes: > Aim for completeness for invalidating everything > and mark state pointers stale. > > Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> nak, this breaks iris. indirect state disable removes push constant state from the render context, not just invalidating it emphemerally. iris is depending on that state to persist.
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index b47230583494..7807f53eae18 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -4585,6 +4585,7 @@ static int gen12_emit_flush_render(struct i915_request *request, flags |= PIPE_CONTROL_TLB_INVALIDATE; flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_INDIRECT_STATE_DISABLE; flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
Aim for completeness for invalidating everything and mark state pointers stale. Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 1 + 1 file changed, 1 insertion(+)