| Message ID | 20200430154735.22434-7-mika.kuoppala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate" | expand |
Quoting Mika Kuoppala (2020-04-30 16:47:33) > Flush enable bit is a sync point which makes this > pipecontrol to wait that everything on a previous > pipe control are flushed. Enable it to make > sure that our invalidates doesn't overlap. Not sold. We terminated the previous context with a serialising flush; the pipe should be idle... But what about preemption, hmm? But then you have preemption between batches past the invalidate point, and so it must all be safely restored from context. So the primarily concern here is with state being overwritten by GTT updates. Still not sold. -Chris
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 7807f53eae18..789efece1fc0 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -4590,6 +4590,8 @@ static int gen12_emit_flush_render(struct i915_request *request, flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_FLUSH_ENABLE; + flags |= PIPE_CONTROL_STORE_DATA_INDEX; flags |= PIPE_CONTROL_QW_WRITE;
Flush enable bit is a sync point which makes this pipecontrol to wait that everything on a previous pipe control are flushed. Enable it to make sure that our invalidates doesn't overlap. Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++ 1 file changed, 2 insertions(+)