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[8/9] drm/i915/gen12: Invalidate media state

Message ID 20200430154735.22434-8-mika.kuoppala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series [1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate" | expand

Commit Message

Mika Kuoppala April 30, 2020, 3:47 p.m. UTC
Treat media state as any other state and invalidate it.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Chris Wilson May 3, 2020, 9:32 p.m. UTC | #1
Quoting Mika Kuoppala (2020-04-30 16:47:34)
> Treat media state as any other state and invalidate it.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 789efece1fc0..859c901c8935 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4583,6 +4583,7 @@  static int gen12_emit_flush_render(struct i915_request *request,
 
 		flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_TLB_INVALIDATE;
+		flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_INDIRECT_STATE_DISABLE;