| Message ID | 20200505000146.2295525-1-d.scott.phillips@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/tgl: Put HDC flush pipe_control bit in the right dword | expand |
D Scott Phillips <d.scott.phillips@intel.com> writes: > Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12 > pipe_control commands. HDC Pipeline flush actually resides in > dword 0, and the bit we were setting in dword 1 was Indirect State > Pointers Disable, which invalidates indirect state in the render > context. This causes failures for userspace, as things like push > constant state gets invalidated. > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Signed-off-by: D Scott Phillips <d.scott.phillips@intel.com> also, Fixes: 4aa0b5d457f5 ("drm/i915/tgl: Add HDC Pipeline Flush")
On Monday, May 4, 2020 5:01:46 PM PDT D Scott Phillips wrote: > Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12 > pipe_control commands. HDC Pipeline flush actually resides in > dword 0, and the bit we were setting in dword 1 was Indirect State > Pointers Disable, which invalidates indirect state in the render > context. This causes failures for userspace, as things like push > constant state gets invalidated. > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Signed-off-by: D Scott Phillips <d.scott.phillips@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine.h | 23 +++++++++++++++++------ > drivers/gpu/drm/i915/gt/intel_lrc.c | 11 ++++++----- > 2 files changed, 23 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h > index 19d0b8830905..8338be338ec8 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h > @@ -241,19 +241,24 @@ void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); > void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine, > struct drm_printer *p); > > -static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset) > +static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset) Great find! It looks like HDC_PIPELINE_FLUSH moved from bit 41 to bit 9 even on Icelake / Gen11 - so it might make sense to call this gen11_emit_pipe_control() and use it on the Icelake functions. That said, i915 never sets HDC_PIPELINE_FLUSH until Gen12, so we don't actually have a bug to fix on Icelake today. But if someone started trying to set it on Gen11, we would have a bug - hence the suggestion. With or without any changes, Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> and thanks so much for tracking this down!
On 05/05/2020 03:09, D Scott Phillips wrote: > D Scott Phillips <d.scott.phillips@intel.com> writes: > >> Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12 >> pipe_control commands. HDC Pipeline flush actually resides in >> dword 0, and the bit we were setting in dword 1 was Indirect State >> Pointers Disable, which invalidates indirect state in the render >> context. This causes failures for userspace, as things like push >> constant state gets invalidated. >> >> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> >> Cc: Chris Wilson <chris@chris-wilson.co.uk> >> Signed-off-by: D Scott Phillips <d.scott.phillips@intel.com> > also, > > Fixes: 4aa0b5d457f5 ("drm/i915/tgl: Add HDC Pipeline Flush") > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx I think Mika sent the same patch in "drm/i915/gen12: Fix HDC pipeline flush". -Lionel
Lionel Landwerlin <lionel.g.landwerlin@intel.com> writes: > On 05/05/2020 03:09, D Scott Phillips wrote: >> D Scott Phillips <d.scott.phillips@intel.com> writes: >> >>> Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12 >>> pipe_control commands. HDC Pipeline flush actually resides in >>> dword 0, and the bit we were setting in dword 1 was Indirect State >>> Pointers Disable, which invalidates indirect state in the render >>> context. This causes failures for userspace, as things like push >>> constant state gets invalidated. >>> >>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> >>> Cc: Chris Wilson <chris@chris-wilson.co.uk> >>> Signed-off-by: D Scott Phillips <d.scott.phillips@intel.com> >> also, >> >> Fixes: 4aa0b5d457f5 ("drm/i915/tgl: Add HDC Pipeline Flush") >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > I think Mika sent the same patch in "drm/i915/gen12: Fix HDC pipeline > flush". > > -Lionel Ah, quite right, I missed it. Ignore this.
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 19d0b8830905..8338be338ec8 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -241,19 +241,24 @@ void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine, struct drm_printer *p); -static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset) +static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset) { memset(batch, 0, 6 * sizeof(u32)); - batch[0] = GFX_OP_PIPE_CONTROL(6); - batch[1] = flags; + batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0; + batch[1] = flags1; batch[2] = offset; return batch + 6; } +static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset) +{ + return gen12_emit_pipe_control(batch, 0, flags, offset); +} + static inline u32 * -gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags) +gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1) { /* We're using qword write, offset should be aligned to 8 bytes. */ GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8)); @@ -262,8 +267,8 @@ gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags) * need a prior CS_STALL, which is emitted by the flush * following the batch. */ - *cs++ = GFX_OP_PIPE_CONTROL(6); - *cs++ = flags | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB; + *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0; + *cs++ = flags1 | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB; *cs++ = gtt_offset; *cs++ = 0; *cs++ = value; @@ -273,6 +278,12 @@ gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags) return cs; } +static inline u32 * +gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags) +{ + return gen12_emit_ggtt_write_rcs(cs, value, gtt_offset, 0, flags); +} + static inline u32 * gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags) { diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index d4ef344657b0..af7790ac9f6a 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -4549,6 +4549,7 @@ static int gen12_emit_flush_render(struct i915_request *request, u32 mode) { if (mode & EMIT_FLUSH) { + u32 flags0 = 0; u32 flags = 0; u32 *cs; @@ -4559,7 +4560,7 @@ static int gen12_emit_flush_render(struct i915_request *request, flags |= PIPE_CONTROL_DEPTH_STALL; flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; flags |= PIPE_CONTROL_FLUSH_ENABLE; - flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH; + flags0 |= PIPE_CONTROL_HDC_PIPELINE_FLUSH; flags |= PIPE_CONTROL_STORE_DATA_INDEX; flags |= PIPE_CONTROL_QW_WRITE; @@ -4570,7 +4571,7 @@ static int gen12_emit_flush_render(struct i915_request *request, if (IS_ERR(cs)) return PTR_ERR(cs); - cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); + cs = gen12_emit_pipe_control(cs, flags0, flags, LRC_PPHWSP_SCRATCH_ADDR); intel_ring_advance(request, cs); } @@ -4762,9 +4763,10 @@ static u32 *gen12_emit_fini_breadcrumb(struct i915_request *request, u32 *cs) static u32 * gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) { - cs = gen8_emit_ggtt_write_rcs(cs, + cs = gen12_emit_ggtt_write_rcs(cs, request->fence.seqno, i915_request_active_timeline(request)->hwsp_offset, + PIPE_CONTROL_HDC_PIPELINE_FLUSH, PIPE_CONTROL_CS_STALL | PIPE_CONTROL_TILE_CACHE_FLUSH | PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | @@ -4772,8 +4774,7 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) /* Wa_1409600907:tgl */ PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_DC_FLUSH_ENABLE | - PIPE_CONTROL_FLUSH_ENABLE | - PIPE_CONTROL_HDC_PIPELINE_FLUSH); + PIPE_CONTROL_FLUSH_ENABLE); return gen12_emit_fini_breadcrumb_footer(request, cs); }
Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12 pipe_control commands. HDC Pipeline flush actually resides in dword 0, and the bit we were setting in dword 1 was Indirect State Pointers Disable, which invalidates indirect state in the render context. This causes failures for userspace, as things like push constant state gets invalidated. Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: D Scott Phillips <d.scott.phillips@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine.h | 23 +++++++++++++++++------ drivers/gpu/drm/i915/gt/intel_lrc.c | 11 ++++++----- 2 files changed, 23 insertions(+), 11 deletions(-)