From patchwork Thu May 14 12:38:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11548623 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A80E960D for ; Thu, 14 May 2020 12:38:47 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 908B120722 for ; Thu, 14 May 2020 12:38:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 908B120722 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 180786EB32; Thu, 14 May 2020 12:38:47 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3697E6EB32 for ; Thu, 14 May 2020 12:38:45 +0000 (UTC) IronPort-SDR: T7Q8usbHLdvULBMvGJJgY1CouXOG2hgziv7gCCn5D5Lk7T6sCTyvgvPX9l7lY6pfzOXQwyBomJ M4vtFQF1URhw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2020 05:38:44 -0700 IronPort-SDR: p/MhGKW2V8xltSce/h0FyaCa91XiJyVkpA9X33QlSqimdzkCEcw/SRV8HIYf8RumDVhy/NDXrg UkOyjlGZOOjQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,391,1583222400"; d="scan'208";a="252067962" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga007.fm.intel.com with SMTP; 14 May 2020 05:38:42 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 14 May 2020 15:38:41 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 14 May 2020 15:38:37 +0300 Message-Id: <20200514123838.3017-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514123838.3017-1-ville.syrjala@linux.intel.com> References: <20200514123838.3017-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 2/3] drm/i915: Document our lackluster FSB frequency readout X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Document the fact that we aren't reading out the actual FSB frequency but rather just the state of the FSB straps. Some BIOSen allow you to configure the two independently. So if someone sets the two up in an inconsistent manner we'll get the wrong answer here and thus will end up with incorrect aux/pps clock dividers. Alas, proper docs are no longer around so we can't do any better. Signed-off-by: Ville Syrjälä Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/display/intel_cdclk.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index c17cf611625c..d57dfec7e9a5 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2704,7 +2704,16 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv) { u32 clkcfg; - /* hrawclock is 1/4 the FSB frequency */ + /* + * hrawclock is 1/4 the FSB frequency + * + * Note that this only reads the state of the FSB + * straps, not the actual FSB frequency. Some BIOSen + * let you configure each independently. Ideally we'd + * read out the actual FSB frequency but sadly we + * don't know which registers have that information, + * and all the relevant docs have gone to bit heaven :( + */ clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; /* ELK seems to redefine some of the values */