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[166.177.187.115]) by smtp.gmail.com with ESMTPSA id m33sm2406360qtb.88.2020.05.20.06.08.16 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 May 2020 06:08:17 -0700 (PDT) From: Sean Paul To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Wed, 20 May 2020 09:08:08 -0400 Message-Id: <20200520130808.44095-1-sean@poorly.run> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200520064602.GA20133@intel.com> References: <20200520064602.GA20133@intel.com> Subject: [Intel-gfx] [PATCH v2] drm/i915/hdcp: Add additional R0' wait X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: seanpaul@chromium.org MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Sean Paul We're seeing some R0' mismatches in the field, particularly with repeaters. I'm guessing the (already lenient) 300ms wait time isn't enough for some setups. So add an additional wait when R0' is mismatched. Signed-off-by: Sean Paul Changes in v2: - Actually add the delay in R0` wait (Ram) --- Apologies, v1 was generated from a forward port from the CrOS kernel and patch got confused and put the diff in V' wait instead of R0' wait. Pay closer attention, Sean. drivers/gpu/drm/i915/display/intel_hdcp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 2cbc4619b4ce..3c2d8c0a6da6 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -743,6 +743,9 @@ static int intel_hdcp_auth(struct intel_connector *connector) if (!wait_for(intel_de_read(dev_priv, HDCP_STATUS(dev_priv, cpu_transcoder, port)) & (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) break; + + /* Maybe the sink is lazy, give it some more time */ + usleep_range(10000, 50000); } if (i == tries) {