From patchwork Tue May 26 22:14:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11571451 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1C2301391 for ; Tue, 26 May 2020 22:12:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 05345208DB for ; Tue, 26 May 2020 22:12:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 05345208DB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 148F989BF8; Tue, 26 May 2020 22:12:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 654E36E20F for ; Tue, 26 May 2020 22:12:45 +0000 (UTC) IronPort-SDR: TPvyAkKaGlns48s34AX+mYsMQmhM2WpH7FTf/0mjXkbhef1LPc3uxbZ8Ad6y22wjGuVG8ew19Y KbYMtoziUrJQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2020 15:12:44 -0700 IronPort-SDR: +ALF3DTnu6lyjqEX/VOrt/mZqEEJ/BOQz24ThNbuJfdC5WkZQtdcG4rQMm2kT12mPfMcNXnsyo Pn1BlZ5vTmGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,439,1583222400"; d="scan'208";a="310381867" Received: from josouza-mobl2.jf.intel.com (HELO josouza-MOBL2.intel.com) ([10.24.14.40]) by FMSMGA003.fm.intel.com with ESMTP; 26 May 2020 15:12:44 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 26 May 2020 15:14:45 -0700 Message-Id: <20200526221447.64110-4-jose.souza@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200526221447.64110-1-jose.souza@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Add PSR2 software tracking registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This registers will be used to implement PSR2 software tracking. BSpec: 55229 BSpec: 50424 BSpec: 50420 Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 68 ++++++++++++++++++++++++++++++--- 1 file changed, 63 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e9d50fe0f375..6f547e459d30 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4566,6 +4566,18 @@ enum { #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) #define PSR2_SU_STATUS_FRAMES 8 +#define _PSR2_MAN_TRK_CTL_A 0x60910 +#define _PSR2_MAN_TRK_CTL_EDP 0x6f910 +#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) +#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) +#define PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK REG_GENMASK(30, 21) +#define PSR2_MAN_TRK_CTL_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK, val) +#define PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK REG_GENMASK(20, 11) +#define PSR2_MAN_TRK_CTL_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK, val) +#define PSR2_MAN_TRK_CTL_SINGLE_FULL_FRAME REG_BIT(3) +#define PSR2_MAN_TRK_CTL_CONTINUOS_FULL_FRAME REG_BIT(2) +#define PSR2_MAN_TRK_CTL_PARTIAL_FRAME_UPDATE REG_BIT(1) + /* VGA port control */ #define ADPA _MMIO(0x61100) #define PCH_ADPA _MMIO(0xe1100) @@ -7129,7 +7141,52 @@ enum { #define PLANE_COLOR_CTL(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) -#/* SKL new cursor registers */ +#define _PLANE_SEL_FETCH_BASE_1_A 0x70890 +#define _PLANE_SEL_FETCH_BASE_2_A 0x708B0 +#define _PLANE_SEL_FETCH_BASE_3_A 0x708D0 +#define _PLANE_SEL_FETCH_BASE_4_A 0x708F0 +#define _PLANE_SEL_FETCH_BASE_5_A 0x70920 +#define _PLANE_SEL_FETCH_BASE_6_A 0x70940 +#define _PLANE_SEL_FETCH_BASE_7_A 0x70960 +#define _PLANE_SEL_FETCH_BASE_CUR_A 0x70880 +#define _PLANE_SEL_FETCH_BASE_1_B 0x70990 + +#define _PLANE_SEL_FETCH_BASE_A(plane) _PICK(plane, \ + _PLANE_SEL_FETCH_BASE_1_A, \ + _PLANE_SEL_FETCH_BASE_2_A, \ + _PLANE_SEL_FETCH_BASE_3_A, \ + _PLANE_SEL_FETCH_BASE_4_A, \ + _PLANE_SEL_FETCH_BASE_5_A, \ + _PLANE_SEL_FETCH_BASE_6_A, \ + _PLANE_SEL_FETCH_BASE_7_A, \ + _PLANE_SEL_FETCH_BASE_CUR_A) +#define _PLANE_SEL_FETCH_BASE_1(pipe) _PIPE(pipe, _PLANE_SEL_FETCH_BASE_1_A, _PLANE_SEL_FETCH_BASE_1_A) +#define PLANE_SEL_FETCH_BASE(pipe, plane) (_PLANE_SEL_FETCH_BASE_1(pipe) - \ + _PLANE_SEL_FETCH_BASE_1_A + \ + _PLANE_SEL_FETCH_BASE_A(plane)) + +#define _PLANE_SEL_FETCH_CTL_1_A 0x70890 +#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ + _PLANE_SEL_FETCH_CTL_1_A - \ + _PLANE_SEL_FETCH_BASE_1_A) +#define PLANE_SET_FETCH_CTL_ENABLE REG_BIT(31) + +#define _PLANE_SEL_FETCH_POS_1_A 0x70894 +#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ + _PLANE_SEL_FETCH_POS_1_A - \ + _PLANE_SEL_FETCH_BASE_1_A) + +#define _PLANE_SEL_FETCH_SIZE_1_A 0x70898 +#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ + _PLANE_SEL_FETCH_SIZE_1_A - \ + _PLANE_SEL_FETCH_BASE_1_A) + +#define _PLANE_SEL_FETCH_OFFSET_1_A 0x7089C +#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ + _PLANE_SEL_FETCH_OFFSET_1_A - \ + _PLANE_SEL_FETCH_BASE_1_A) + +/* SKL new cursor registers */ #define _CUR_BUF_CFG_A 0x7017c #define _CUR_BUF_CFG_B 0x7117c #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) @@ -7775,11 +7832,12 @@ enum { # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) -#define CHICKEN_PAR1_1 _MMIO(0x42080) +#define CHICKEN_PAR1_1 _MMIO(0x42080) #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) -#define DPA_MASK_VBLANK_SRD (1 << 15) -#define FORCE_ARB_IDLE_PLANES (1 << 14) -#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) +#define DPA_MASK_VBLANK_SRD (1 << 15) +#define FORCE_ARB_IDLE_PLANES (1 << 14) +#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) +#define IGNORE_PSR2_HW_TRACKING (1 << 1) #define CHICKEN_PAR2_1 _MMIO(0x42090) #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)