| Message ID | 20200607181840.13536-10-hdegoede@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API | expand |
On Sun, Jun 07, 2020 at 08:18:34PM +0200, Hans de Goede wrote: > The pwm-crc code is using 2 different enable bits: > 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) > 2. bit 0 of the BACKLIGHT_EN register > > So far we've kept the PWM_OUTPUT_ENABLE bit set when disabling the PWM, > this commit makes crc_pwm_disable() clear it on disable and makes > crc_pwm_enable() set it again on re-enable. > > This should disable the internal (divided) PWM clock and tri-state the > PWM output pin when disabled, saving some power. ... > +static int crc_pwm_calc_clk_div(int period_ns) > +{ > + int clk_div; > + > + clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); > + /* clk_div 1 - 128, maps to register values 0-127 */ > + if (clk_div > 0) > + clk_div--; > + > + return clk_div; > +} You can reduce ping-pong format of the series if you introduced this helper in the patch that adds -1 to clock divisor.
On Sun, Jun 07, 2020 at 08:18:34PM +0200, Hans de Goede wrote: > The pwm-crc code is using 2 different enable bits: > 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) > 2. bit 0 of the BACKLIGHT_EN register > > So far we've kept the PWM_OUTPUT_ENABLE bit set when disabling the PWM, > this commit makes crc_pwm_disable() clear it on disable and makes > crc_pwm_enable() set it again on re-enable. > > This should disable the internal (divided) PWM clock and tri-state the > PWM output pin when disabled, saving some power. It would be great if you could also document that disabling the PWM makes the output tri-state. There are a few drivers that have a "Limitations" section at their top. Describing that there (in the same format) would be the right place. Also note that according to Thierry's conception getting a (driven) inactive output is the right thing for a disabled PWM. Best regards Uwe
Hi, On 6/12/20 12:20 AM, Uwe Kleine-König wrote: > On Sun, Jun 07, 2020 at 08:18:34PM +0200, Hans de Goede wrote: >> The pwm-crc code is using 2 different enable bits: >> 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) >> 2. bit 0 of the BACKLIGHT_EN register >> >> So far we've kept the PWM_OUTPUT_ENABLE bit set when disabling the PWM, >> this commit makes crc_pwm_disable() clear it on disable and makes >> crc_pwm_enable() set it again on re-enable. >> >> This should disable the internal (divided) PWM clock and tri-state the >> PWM output pin when disabled, saving some power. > > It would be great if you could also document that disabling the PWM > makes the output tri-state. There are a few drivers that have a > "Limitations" section at their top. Describing that there (in the same > format) would be the right place. > > Also note that according to Thierry's conception getting a (driven) > inactive output is the right thing for a disabled PWM. Hmm, the tri-state thing is an assumption from my side and we don't have any docs for this PWM controller, so I'm not sure at all if that is true. So I think it will be better to just drop the tri-state bit from the commit msg for the next version. Regards, Hans
diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index ef49a6e3c4d6..53734bcf67e1 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -41,10 +41,24 @@ static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc) return container_of(pc, struct crystalcove_pwm, chip); } +static int crc_pwm_calc_clk_div(int period_ns) +{ + int clk_div; + + clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); + /* clk_div 1 - 128, maps to register values 0-127 */ + if (clk_div > 0) + clk_div--; + + return clk_div; +} + static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm) { struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); + int div = crc_pwm_calc_clk_div(pwm_get_period(pwm)); + regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, div | PWM_OUTPUT_ENABLE); regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1); return 0; @@ -53,8 +67,10 @@ static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm) static void crc_pwm_disable(struct pwm_chip *c, struct pwm_device *pwm) { struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); + int div = crc_pwm_calc_clk_div(pwm_get_period(pwm)); regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0); + regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, div); } static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, @@ -70,16 +86,10 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, } if (pwm_get_period(pwm) != period_ns) { - int clk_div; + int clk_div = crc_pwm_calc_clk_div(period_ns); /* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */ regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0); - - clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); - /* clk_div 1 - 128, maps to register values 0-127 */ - if (clk_div > 0) - clk_div--; - regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, clk_div | PWM_OUTPUT_ENABLE); }
The pwm-crc code is using 2 different enable bits: 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) 2. bit 0 of the BACKLIGHT_EN register So far we've kept the PWM_OUTPUT_ENABLE bit set when disabling the PWM, this commit makes crc_pwm_disable() clear it on disable and makes crc_pwm_enable() set it again on re-enable. This should disable the internal (divided) PWM clock and tri-state the PWM output pin when disabled, saving some power. Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- drivers/pwm/pwm-crc.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-)