diff mbox series

[3/3] drm/i915/display: Implement new combo phy initialization step

Message ID 20200623225934.147326-1-jose.souza@intel.com (mailing list archive)
State New, archived
Headers show
Series [1/2] drm/i915/display/rkl: Implement WA 14011471926 | expand

Commit Message

Souza, Jose June 23, 2020, 10:59 p.m. UTC 
This is new step that was recently added to the combo phy
initialization.

BSpec: 49291
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 .../gpu/drm/i915/display/intel_combo_phy.c    | 25 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h               |  7 ++++++
 2 files changed, 32 insertions(+)

Comments

Lucas De Marchi June 23, 2020, 11:03 p.m. UTC | #1 
On Tue, Jun 23, 2020 at 3:58 PM José Roberto de Souza
<jose.souza@intel.com> wrote:
>
> This is new step that was recently added to the combo phy
> initialization.
>
> BSpec: 49291
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_combo_phy.c    | 25 +++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h               |  7 ++++++
>  2 files changed, 32 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 38496d2e37fc..585504ad3e65 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -270,6 +270,18 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
>         if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) && phy == PHY_B)
>                 return false;
>
> +       if (INTEL_GEN(dev_priv) >= 12) {
> +               ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_GRP(phy),
> +                                    ICL_PORT_TX_DW8_ODCC_CLK_SEL |
> +                                    ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
> +                                    ICL_PORT_TX_DW8_ODCC_CLK_SEL |
> +                                    ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
> +
> +               ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_GRP(phy),
> +                                    DCC_MODE_SELECT_MASK,
> +                                    DCC_MODE_SELECT_CONTINUOSLY);
> +       }
> +
>         ret = cnl_verify_procmon_ref_values(dev_priv, phy);
>
>         if (phy_is_master(dev_priv, phy)) {
> @@ -381,6 +393,19 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
>                 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
>
>  skip_phy_misc:
> +               if (INTEL_GEN(dev_priv) >= 12) {
> +                       val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_GRP(phy));
> +                       val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
> +                       val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
> +                       val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
> +                       intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
> +
> +                       val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_GRP(phy));
> +                       val &= ~DCC_MODE_SELECT_MASK;
> +                       val |= DCC_MODE_SELECT_CONTINUOSLY;
> +                       intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
> +               }

any reason not to use intel_de_rmw() in these 2?

Lucas De Marchi
> +
>                 cnl_set_procmon_ref_values(dev_priv, phy);
>
>                 if (phy_is_master(dev_priv, phy)) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6938f4d251ae..a882e6329f1b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1985,6 +1985,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define ICL_PORT_PCS_DW1_AUX(phy)      _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
>  #define ICL_PORT_PCS_DW1_GRP(phy)      _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
>  #define ICL_PORT_PCS_DW1_LN0(phy)      _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
> +#define   DCC_MODE_SELECT_MASK         (0x3 << 20)
> +#define   DCC_MODE_SELECT_CONTINUOSLY  (0x3 << 20)
>  #define   COMMON_KEEPER_EN             (1 << 26)
>  #define   LATENCY_OPTIM_MASK           (0x3 << 2)
>  #define   LATENCY_OPTIM_VAL(x)         ((x) << 2)
> @@ -2083,6 +2085,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define   N_SCALAR(x)                  ((x) << 24)
>  #define   N_SCALAR_MASK                        (0x7F << 24)
>
> +#define ICL_PORT_TX_DW8_GRP(phy)               _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
> +#define ICL_PORT_TX_DW8_ODCC_CLK_SEL           REG_BIT(31)
> +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK  REG_GENMASK(30, 29)
> +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2  REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
> +
>  #define _ICL_DPHY_CHKN_REG                     0x194
>  #define ICL_DPHY_CHKN(port)                    _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
>  #define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP     REG_BIT(7)
> --
> 2.27.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Souza, Jose June 23, 2020, 11:09 p.m. UTC | #2 
On Tue, 2020-06-23 at 16:03 -0700, Lucas De Marchi wrote:
> On Tue, Jun 23, 2020 at 3:58 PM José Roberto de Souza
> <jose.souza@intel.com> wrote:
> > This is new step that was recently added to the combo phy
> > initialization.
> > 
> > BSpec: 49291
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_combo_phy.c    | 25 +++++++++++++++++++
> >  drivers/gpu/drm/i915/i915_reg.h               |  7 ++++++
> >  2 files changed, 32 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> > index 38496d2e37fc..585504ad3e65 100644
> > --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> > @@ -270,6 +270,18 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
> >         if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) && phy == PHY_B)
> >                 return false;
> > 
> > +       if (INTEL_GEN(dev_priv) >= 12) {
> > +               ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_GRP(phy),
> > +                                    ICL_PORT_TX_DW8_ODCC_CLK_SEL |
> > +                                    ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
> > +                                    ICL_PORT_TX_DW8_ODCC_CLK_SEL |
> > +                                    ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
> > +
> > +               ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_GRP(phy),
> > +                                    DCC_MODE_SELECT_MASK,
> > +                                    DCC_MODE_SELECT_CONTINUOSLY);
> > +       }
> > +
> >         ret = cnl_verify_procmon_ref_values(dev_priv, phy);
> > 
> >         if (phy_is_master(dev_priv, phy)) {
> > @@ -381,6 +393,19 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
> >                 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
> > 
> >  skip_phy_misc:
> > +               if (INTEL_GEN(dev_priv) >= 12) {
> > +                       val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_GRP(phy));
> > +                       val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
> > +                       val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
> > +                       val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
> > +                       intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
> > +
> > +                       val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_GRP(phy));
> > +                       val &= ~DCC_MODE_SELECT_MASK;
> > +                       val |= DCC_MODE_SELECT_CONTINUOSLY;
> > +                       intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
> > +               }
> 
> any reason not to use intel_de_rmw() in these 2?

No reason at all, will change to intel_de_rmw().Thanks

> 
> Lucas De Marchi
> > +
> >                 cnl_set_procmon_ref_values(dev_priv, phy);
> > 
> >                 if (phy_is_master(dev_priv, phy)) {
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 6938f4d251ae..a882e6329f1b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1985,6 +1985,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >  #define ICL_PORT_PCS_DW1_AUX(phy)      _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
> >  #define ICL_PORT_PCS_DW1_GRP(phy)      _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
> >  #define ICL_PORT_PCS_DW1_LN0(phy)      _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
> > +#define   DCC_MODE_SELECT_MASK         (0x3 << 20)
> > +#define   DCC_MODE_SELECT_CONTINUOSLY  (0x3 << 20)
> >  #define   COMMON_KEEPER_EN             (1 << 26)
> >  #define   LATENCY_OPTIM_MASK           (0x3 << 2)
> >  #define   LATENCY_OPTIM_VAL(x)         ((x) << 2)
> > @@ -2083,6 +2085,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >  #define   N_SCALAR(x)                  ((x) << 24)
> >  #define   N_SCALAR_MASK                        (0x7F << 24)
> > 
> > +#define ICL_PORT_TX_DW8_GRP(phy)               _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
> > +#define ICL_PORT_TX_DW8_ODCC_CLK_SEL           REG_BIT(31)
> > +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK  REG_GENMASK(30, 29)
> > +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2  REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
> > +
> >  #define _ICL_DPHY_CHKN_REG                     0x194
> >  #define ICL_DPHY_CHKN(port)                    _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
> >  #define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP     REG_BIT(7)
> > --
> > 2.27.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 38496d2e37fc..585504ad3e65 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -270,6 +270,18 @@  static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 	if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) && phy == PHY_B)
 		return false;
 
+	if (INTEL_GEN(dev_priv) >= 12) {
+		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_GRP(phy),
+				     ICL_PORT_TX_DW8_ODCC_CLK_SEL |
+				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
+				     ICL_PORT_TX_DW8_ODCC_CLK_SEL |
+				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
+
+		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_GRP(phy),
+				     DCC_MODE_SELECT_MASK,
+				     DCC_MODE_SELECT_CONTINUOSLY);
+	}
+
 	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
 
 	if (phy_is_master(dev_priv, phy)) {
@@ -381,6 +393,19 @@  static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 		intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
 
 skip_phy_misc:
+		if (INTEL_GEN(dev_priv) >= 12) {
+			val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_GRP(phy));
+			val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
+			val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
+			val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
+			intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
+
+			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_GRP(phy));
+			val &= ~DCC_MODE_SELECT_MASK;
+			val |= DCC_MODE_SELECT_CONTINUOSLY;
+			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
+		}
+
 		cnl_set_procmon_ref_values(dev_priv, phy);
 
 		if (phy_is_master(dev_priv, phy)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6938f4d251ae..a882e6329f1b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1985,6 +1985,8 @@  static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define ICL_PORT_PCS_DW1_AUX(phy)	_MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
 #define ICL_PORT_PCS_DW1_GRP(phy)	_MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
 #define ICL_PORT_PCS_DW1_LN0(phy)	_MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
+#define   DCC_MODE_SELECT_MASK		(0x3 << 20)
+#define   DCC_MODE_SELECT_CONTINUOSLY	(0x3 << 20)
 #define   COMMON_KEEPER_EN		(1 << 26)
 #define   LATENCY_OPTIM_MASK		(0x3 << 2)
 #define   LATENCY_OPTIM_VAL(x)		((x) << 2)
@@ -2083,6 +2085,11 @@  static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   N_SCALAR(x)			((x) << 24)
 #define   N_SCALAR_MASK			(0x7F << 24)
 
+#define ICL_PORT_TX_DW8_GRP(phy)		_MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
+#define ICL_PORT_TX_DW8_ODCC_CLK_SEL		REG_BIT(31)
+#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK	REG_GENMASK(30, 29)
+#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2	REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
+
 #define _ICL_DPHY_CHKN_REG			0x194
 #define ICL_DPHY_CHKN(port)			_MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
 #define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP	REG_BIT(7)