From patchwork Mon Jun 29 21:20:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11632581 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CF79C138C for ; Mon, 29 Jun 2020 21:19:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B80F820720 for ; Mon, 29 Jun 2020 21:19:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B80F820720 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1551689F9F; Mon, 29 Jun 2020 21:19:34 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id B2F0489F9F for ; Mon, 29 Jun 2020 21:19:32 +0000 (UTC) IronPort-SDR: mMM8+2bLrlMSmGZqX9gLt7l0yzuS/NbtJo8a/XqGcxOZT3RzccUUNIYM/+q7XvSAympGunC/w4 aSfnG++FVW9g== X-IronPort-AV: E=McAfee;i="6000,8403,9666"; a="126210805" X-IronPort-AV: E=Sophos;i="5.75,295,1589266800"; d="scan'208";a="126210805" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2020 14:19:31 -0700 IronPort-SDR: Ao03Id8918I4mR2OKjGxggBp5wGzWBYlnb9N9faGK+y2v5APU8Q+BoYkUOJ5/OzO/zZSUnjY/a JC2KpEQzQtrQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,295,1589266800"; d="scan'208";a="312172494" Received: from anuragpi-mobl.amr.corp.intel.com (HELO josouza-MOBL2.amr.corp.intel.com) ([10.254.46.142]) by orsmga008.jf.intel.com with ESMTP; 29 Jun 2020 14:19:31 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Mon, 29 Jun 2020 14:20:58 -0700 Message-Id: <20200629212059.108460-1-jose.souza@intel.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Implement WA 18011464164 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This fix some possible corruptions. BSpec: 52755 BSpec: 52890 Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 8 +++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 284af0c6439c..797e036fa695 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4170,6 +4170,9 @@ enum { #define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560) #define CGPSF_CLKGATE_DIS (1 << 3) +#define SLICE_UNIT_LEVEL_CLOCK_GATING_CTL _MMIO(0x94D8) +#define GS_UNIT_CLOCK_GATING_DIS REG_BIT(24) + /* * Display engine regs */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2a32d6230795..86408173c435 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7113,7 +7113,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(POWERGATE_ENABLE, I915_READ(POWERGATE_ENABLE) | vd_pg_enable); - /* Wa_1409825376:tgl (pre-prod)*/ + /* Wa_1409825376:tgl (pre-prod) */ if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0)) I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) | TGL_VRH_GATING_DIS); @@ -7121,6 +7121,12 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) /* Wa_14011059788:tgl */ intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN, 0, DFR_DISABLE); + + /* Wa_18011464164:tgl */ + if (IS_TGL_REVID(dev_priv, TGL_REVID_B0, TGL_REVID_B0)) + intel_uncore_rmw(&dev_priv->uncore, + SLICE_UNIT_LEVEL_CLOCK_GATING_CTL, 0, + GS_UNIT_CLOCK_GATING_DIS); } static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)