From patchwork Thu Jul 9 12:33:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 11654351 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D1CFB14B7 for ; Thu, 9 Jul 2020 12:33:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B057D20708 for ; Thu, 9 Jul 2020 12:33:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=ffwll.ch header.i=@ffwll.ch header.b="FT1zeqK0" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B057D20708 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ffwll.ch Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 501A06E42F; Thu, 9 Jul 2020 12:33:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3DDA06E42F for ; Thu, 9 Jul 2020 12:33:52 +0000 (UTC) Received: by mail-wm1-x342.google.com with SMTP id f139so1617390wmf.5 for ; Thu, 09 Jul 2020 05:33:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9ml7yu61orPGiyeLHj7KPJdBGRuwIj4VGf7RIdg6+6E=; b=FT1zeqK0F6re7x3hxU6WuwKnuhLdZTTGsE6uj0ZmBrbf9TVkVqTK3LOGBYbBEjYddX UQxsmufvcNCR+EiwLcPUmPYWFaC5pZ5CGfGNvzGthBXT2lli8Ur+GfzSgeLxXbdC//jm w7Dqku33+bwbEzRQvB6e/WItr0k784kTvA0/0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9ml7yu61orPGiyeLHj7KPJdBGRuwIj4VGf7RIdg6+6E=; b=QBLyCPF6p2ff3wuG2BS6SIO/Vxyj/0LSsR/0KBF+pjxK9oGVt9vQg2KBPxNbVS3RVL gTJ6q5UrR3PQD0O3i4txZKyUuAZ5qvbbyZP+3svXeiluDh6US7Uchz5w1yQL6oTEMbcB X93h1fLekhihHXlAw4w4NhWN/pS1PGhViWy7AtpQOVW9NzdS8djcZETrEs4LLJHdSZ99 sRvA82AQ7PfCcSh6fxOOgif3lGbzkcD6w04sGBXL5MRzxotcZms7SRXINb1ppCiuLcvH OGgOkxzpHuhZp9OVpbDhDCojyLhoYP24SU0wo6H4Jcb8m0ed9ZtcUmLfm6aTpZcNE+SM 0S0w== X-Gm-Message-State: AOAM5302tW8GgPVULt16VNraCFcSSyP+MMi2Wyo4PL0HvH4q+R5slast rt1Kdw0RLNgFkj4j/WDq/hxxtQ== X-Google-Smtp-Source: ABdhPJyW1X39siqvN1tXyO+a5xJDhtYxZB7qgF8t/3W1eiXrhQsMLgXCOAKI1Lx9mgsJn2P0+ZV+SQ== X-Received: by 2002:a7b:c313:: with SMTP id k19mr14181981wmj.67.1594298030902; Thu, 09 Jul 2020 05:33:50 -0700 (PDT) Received: from phenom.ffwll.local ([2a02:168:57f4:0:efd0:b9e5:5ae6:c2fa]) by smtp.gmail.com with ESMTPSA id o205sm4925347wme.24.2020.07.09.05.33.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2020 05:33:50 -0700 (PDT) From: Daniel Vetter To: DRI Development Date: Thu, 9 Jul 2020 14:33:38 +0200 Message-Id: <20200709123339.547390-1-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200707201229.472834-4-daniel.vetter@ffwll.ch> References: <20200707201229.472834-4-daniel.vetter@ffwll.ch> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Stone , linux-rdma@vger.kernel.org, Daniel Vetter , Intel Graphics Development , amd-gfx@lists.freedesktop.org, Chris Wilson , linaro-mm-sig@lists.linaro.org, Steve Pronovost , Daniel Vetter , Jesse Natalie , Felix Kuehling , Thomas Hellstrom , linux-media@vger.kernel.org, =?utf-8?q?Christian_K=C3=B6nig?= , Mika Kuoppala Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Comes up every few years, gets somewhat tedious to discuss, let's write this down once and for all. What I'm not sure about is whether the text should be more explicit in flat out mandating the amdkfd eviction fences for long running compute workloads or workloads where userspace fencing is allowed. v2: Now with dot graph! v3: Typo (Dave Airlie) Acked-by: Christian König Acked-by: Daniel Stone Cc: Jesse Natalie Cc: Steve Pronovost Cc: Jason Ekstrand Cc: Felix Kuehling Cc: Mika Kuoppala Cc: Thomas Hellstrom Cc: linux-media@vger.kernel.org Cc: linaro-mm-sig@lists.linaro.org Cc: linux-rdma@vger.kernel.org Cc: amd-gfx@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Cc: Chris Wilson Cc: Maarten Lankhorst Cc: Christian König Signed-off-by: Daniel Vetter Reviewed-by: Maarten Lankhorst Acked-by: Jason Ekstrand Reviewed-by: Thomas Hellstrom --- Documentation/driver-api/dma-buf.rst | 70 ++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst index f8f6decde359..100bfd227265 100644 --- a/Documentation/driver-api/dma-buf.rst +++ b/Documentation/driver-api/dma-buf.rst @@ -178,3 +178,73 @@ DMA Fence uABI/Sync File .. kernel-doc:: include/linux/sync_file.h :internal: +Indefinite DMA Fences +~~~~~~~~~~~~~~~~~~~~ + +At various times &dma_fence with an indefinite time until dma_fence_wait() +finishes have been proposed. Examples include: + +* Future fences, used in HWC1 to signal when a buffer isn't used by the display + any longer, and created with the screen update that makes the buffer visible. + The time this fence completes is entirely under userspace's control. + +* Proxy fences, proposed to handle &drm_syncobj for which the fence has not yet + been set. Used to asynchronously delay command submission. + +* Userspace fences or gpu futexes, fine-grained locking within a command buffer + that userspace uses for synchronization across engines or with the CPU, which + are then imported as a DMA fence for integration into existing winsys + protocols. + +* Long-running compute command buffers, while still using traditional end of + batch DMA fences for memory management instead of context preemption DMA + fences which get reattached when the compute job is rescheduled. + +Common to all these schemes is that userspace controls the dependencies of these +fences and controls when they fire. Mixing indefinite fences with normal +in-kernel DMA fences does not work, even when a fallback timeout is included to +protect against malicious userspace: + +* Only the kernel knows about all DMA fence dependencies, userspace is not aware + of dependencies injected due to memory management or scheduler decisions. + +* Only userspace knows about all dependencies in indefinite fences and when + exactly they will complete, the kernel has no visibility. + +Furthermore the kernel has to be able to hold up userspace command submission +for memory management needs, which means we must support indefinite fences being +dependent upon DMA fences. If the kernel also support indefinite fences in the +kernel like a DMA fence, like any of the above proposal would, there is the +potential for deadlocks. + +.. kernel-render:: DOT + :alt: Indefinite Fencing Dependency Cycle + :caption: Indefinite Fencing Dependency Cycle + + digraph "Fencing Cycle" { + node [shape=box bgcolor=grey style=filled] + kernel [label="Kernel DMA Fences"] + userspace [label="userspace controlled fences"] + kernel -> userspace [label="memory management"] + userspace -> kernel [label="Future fence, fence proxy, ..."] + + { rank=same; kernel userspace } + } + +This means that the kernel might accidentally create deadlocks +through memory management dependencies which userspace is unaware of, which +randomly hangs workloads until the timeout kicks in. Workloads, which from +userspace's perspective, do not contain a deadlock. In such a mixed fencing +architecture there is no single entity with knowledge of all dependencies. +Thefore preventing such deadlocks from within the kernel is not possible. + +The only solution to avoid dependencies loops is by not allowing indefinite +fences in the kernel. This means: + +* No future fences, proxy fences or userspace fences imported as DMA fences, + with or without a timeout. + +* No DMA fences that signal end of batchbuffer for command submission where + userspace is allowed to use userspace fencing or long running compute + workloads. This also means no implicit fencing for shared buffers in these + cases.