From patchwork Tue Sep 1 01:09:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11747153 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9D5881709 for ; Tue, 1 Sep 2020 01:06:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 861AD20707 for ; Tue, 1 Sep 2020 01:06:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 861AD20707 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 964456E554; Tue, 1 Sep 2020 01:06:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id E8F066E536 for ; Tue, 1 Sep 2020 01:06:41 +0000 (UTC) IronPort-SDR: ugYzNUYFXtjhwqbMpbU3QlSmNgfaM399eKHGEW/WsQYfehApNfZcuFxM6O3lPtyURhJ7pHTnT3 lZPFnpfTwKIQ== X-IronPort-AV: E=McAfee;i="6000,8403,9730"; a="156343633" X-IronPort-AV: E=Sophos;i="5.76,376,1592895600"; d="scan'208";a="156343633" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2020 18:06:41 -0700 IronPort-SDR: 4cKXtIgMT3MEcZ+/Ldiiu+YKOtG81EMd7UHk1aQK6oJFk9wH0UoP3ucMzXxeSvbQggeGxpHe6+ qtq0kHLjVUNw== X-IronPort-AV: E=Sophos;i="5.76,376,1592895600"; d="scan'208";a="476977347" Received: from josouza-mobl2.jf.intel.com (HELO josouza-MOBL2.intel.com) ([10.24.14.51]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2020 18:06:40 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Mon, 31 Aug 2020 18:09:22 -0700 Message-Id: <20200901010924.235808-2-jose.souza@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200901010924.235808-1-jose.souza@intel.com> References: <20200901010924.235808-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/display: Fix state of PSR2 sub features X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In case PSR2 is disabled by debugfs dc3co_enabled and psr2_sel_fetch_enabled were still being set causing some code paths to be executed were it should not. We have tests for PSR1 and PSR2 so keep those features disabled when PSR1 is active but PSR2 is supported is important. Cc: Gwan-gyeong Mun Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 4e09ae61d4aa..6698d0209879 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -962,12 +962,14 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); dev_priv->psr.busy_frontbuffer_bits = 0; dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; - dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline; + dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline && + dev_priv->psr.psr2_enabled; dev_priv->psr.transcoder = crtc_state->cpu_transcoder; /* DC5/DC6 requires at least 6 idle frames */ val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); dev_priv->psr.dc3co_exit_delay = val; - dev_priv->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; + dev_priv->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch && + dev_priv->psr.psr2_enabled; /* * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR @@ -1178,7 +1180,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st struct i915_psr *psr = &dev_priv->psr; if (!HAS_PSR2_SEL_FETCH(dev_priv) || - !crtc_state->enable_psr2_sel_fetch) + !dev_priv->psr.psr2_sel_fetch_enabled) return; intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(psr->transcoder), @@ -1189,8 +1191,9 @@ void intel_psr2_sel_fetch_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - if (!crtc_state->enable_psr2_sel_fetch) + if (!dev_priv->psr.psr2_sel_fetch_enabled) return; crtc_state->psr2_man_track_ctl = PSR2_MAN_TRK_CTL_ENABLE |